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[209.51.188.17]) by mx.google.com with ESMTPS id w10-20020a05620a424a00b006bc3fa8f6e6si7872806qko.663.2022.09.06.03.59.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Sep 2022 03:59:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jaDTJmdQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVWJA-0003x3-Iz for patch@linaro.org; Tue, 06 Sep 2022 06:59:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVVeV-0003AQ-Gk for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:17:55 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:34383) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVVeT-0005B2-De for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:17:55 -0400 Received: by mail-wr1-x433.google.com with SMTP id e13so14708168wrm.1 for ; Tue, 06 Sep 2022 03:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=MskuRXi73/CxTUiKObOD3XbTcWN+OLxkC/iFVWRr7cY=; b=jaDTJmdQQJ4e0JcMpMbkzEDWqAMtseJhX8p+t91Sf7qCSEAckDtss0WnkDu6yddr/2 Cw5Lh3nc3GrKjm3BNJCRAPpfBqOeiz4biKhJmS92ykL1I8yCOVjWEkAro21xAx6C8px0 9fH8/WsXytuoLRkCEAWnFZeBMQBM05tG4Cpa5HYnAttQ8SMOw64uOwwUhEHczp3CHr2R kRHO57QHU81JYZ2rKqb4qqFeODrJQF9GfrnJc8mWk37OPd8cSvCvWviFwqOKguaoA0QT vNKbPJT5bWAIXJXtWgGuJXWZ7XbLTis6yusCXfGraZfoVD79cqREIIAj2RDtatYBIrLb KOnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=MskuRXi73/CxTUiKObOD3XbTcWN+OLxkC/iFVWRr7cY=; b=l9ZrKPexP5wfrpdA9KRhzbC+z82zculdKT/gBMtEBY8mS8d+5wPQhpvNcOihEZHNUN bdu4J6Z80ObkAKcb6RZw2RIv/r0b6Bui9/3Bskrhgr45Kmz+BrUPAUsPvYyjWR9FpUvE 7zYxdgSCQnzzN/ixINaliMGL+/J/vYrQRVjhvxep8eyVnTcF2RYVW6ObVIY7fmfh3SSs H0G8uUhh3Sa1y8aRldZNsapzFMDczu01frctcpM4/eXWzWuLXNV7gDyljYTKqDGOt9d5 P1VU8pmZKVlV6Nm+Ix3VhiQnMgzkl51q4knoRIKeY5b5blrIrHfSIvJuomDP/Fib9Pzb jvuA== X-Gm-Message-State: ACgBeo1+VKhmgcDNidzjP3m35WPcSFxgV6k2JsNUhOMzHAgAHjvDG6gR 12r1rgPR2AOm40l7sdkB6BV0GN5mvlQ5Z6ud X-Received: by 2002:a05:6000:1f03:b0:228:6c98:b01 with SMTP id bv3-20020a0560001f0300b002286c980b01mr6282677wrb.250.1662459470845; Tue, 06 Sep 2022 03:17:50 -0700 (PDT) Received: from localhost.localdomain ([2a02:8084:a5c0:5a80:ba98:3a71:8524:e0b1]) by smtp.gmail.com with ESMTPSA id y16-20020a05600c365000b003a62bc1735asm14094361wmq.9.2022.09.06.03.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 03:17:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH v1 02/26] target/s390x: Use tcg_constant_* for DisasCompare Date: Tue, 6 Sep 2022 11:17:23 +0100 Message-Id: <20220906101747.344559-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906101747.344559-1-richard.henderson@linaro.org> References: <20220906101747.344559-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 890d1f1db3..ec43bd7a1f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -830,7 +830,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) c->is_64 = false; c->u.s32.a = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case CC_OP_LTGT_32: case CC_OP_LTUGTU_32: @@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_NZ: case CC_OP_FLOGR: c->u.s64.a = cc_dst; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; break; case CC_OP_LTGT_64: @@ -859,14 +859,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_TM_64: case CC_OP_ICM: c->u.s64.a = tcg_temp_new_i64(); - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); break; case CC_OP_ADDU: case CC_OP_SUBU: c->is_64 = true; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; switch (mask) { case 8 | 2: @@ -889,65 +889,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) switch (mask) { case 0x8 | 0x4 | 0x2: /* cc != 3 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; case 0x8 | 0x4 | 0x1: /* cc != 2 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8 | 0x2 | 0x1: /* cc != 1 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ cond = TCG_COND_EQ; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x8 | 0x4: /* cc < 2 */ cond = TCG_COND_LTU; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8: /* cc == 0 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x2 | 0x1: /* cc != 0 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ cond = TCG_COND_NE; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x4: /* cc == 1 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2 | 0x1: /* cc > 1 */ cond = TCG_COND_GTU; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2: /* cc == 2 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x1: /* cc == 3 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; default: /* CC is masked by something else: (8 >> cc) & mask. */ cond = TCG_COND_NE; c->g1 = false; - c->u.s32.a = tcg_const_i32(8); - c->u.s32.b = tcg_const_i32(0); - tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op); + c->u.s32.a = tcg_temp_new_i32(); + c->u.s32.b = tcg_constant_i32(0); + tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask); break; } @@ -1604,7 +1604,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, regs[r1], 1); store_reg32_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1628,7 +1628,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, t, 1); store_reg32h_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1649,7 +1649,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a = regs[r1]; - c.u.s64.b = tcg_const_i64(0); + c.u.s64.b = tcg_constant_i64(0); return help_branch(s, &c, is_imm, imm, o->in2); }