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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id z6-20020a63e106000000b0042a2777550dsm7017419pgh.47.2022.08.22.15.37.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 15:37:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/6] target/i386: Define XMMReg and access macros Date: Mon, 22 Aug 2022 15:37:17 -0700 Message-Id: <20220822223722.1697758-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822223722.1697758-1-richard.henderson@linaro.org> References: <20220822223722.1697758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will be used for proper endian adjustments of gvec xmm ops. Signed-off-by: Richard Henderson --- target/i386/cpu.h | 53 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 82004b65b9..81e5abed86 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1233,18 +1233,33 @@ typedef struct SegmentCache { uint32_t flags; } SegmentCache; -#define MMREG_UNION(n, bits) \ - union n { \ - uint8_t _b_##n[(bits)/8]; \ - uint16_t _w_##n[(bits)/16]; \ - uint32_t _l_##n[(bits)/32]; \ - uint64_t _q_##n[(bits)/64]; \ - float32 _s_##n[(bits)/32]; \ - float64 _d_##n[(bits)/64]; \ - } +typedef union MMXReg { + uint8_t _b_MMXReg[64 / 8]; + uint16_t _w_MMXReg[64 / 16]; + uint32_t _l_MMXReg[64 / 32]; + uint64_t _q_MMXReg[64 / 64]; + float32 _s_MMXReg[64 / 32]; + float64 _d_MMXReg[64 / 64]; +} MMXReg; -typedef MMREG_UNION(ZMMReg, 512) ZMMReg; -typedef MMREG_UNION(MMXReg, 64) MMXReg; +typedef union XMMReg { + uint8_t _b_XMMReg[128 / 8]; + uint16_t _w_XMMReg[128 / 16]; + uint32_t _l_XMMReg[128 / 32]; + uint64_t _q_XMMReg[128 / 64]; + float32 _s_XMMReg[128 / 32]; + float64 _d_XMMReg[128 / 64]; +} XMMReg; + +typedef union ZMMReg { + uint8_t _b_ZMMReg[512 / 8]; + uint16_t _w_ZMMReg[512 / 16]; + uint32_t _l_ZMMReg[512 / 32]; + uint64_t _q_ZMMReg[512 / 64]; + float32 _s_ZMMReg[512 / 32]; + float64 _d_ZMMReg[512 / 64]; + XMMReg _x_ZMMReg[512 / 128]; +} ZMMReg; typedef struct BNDReg { uint64_t lb; @@ -1267,6 +1282,14 @@ typedef struct BNDCSReg { #define ZMM_S(n) _s_ZMMReg[15 - (n)] #define ZMM_Q(n) _q_ZMMReg[7 - (n)] #define ZMM_D(n) _d_ZMMReg[7 - (n)] +#define ZMM_X(n) _x_ZMMReg[3 - (n)] + +#define XMM_B(n) _b_XMMReg[15 - (n)] +#define XMM_W(n) _w_XMMReg[7 - (n)] +#define XMM_L(n) _l_XMMReg[3 - (n)] +#define XMM_S(n) _s_XMMReg[3 - (n)] +#define XMM_Q(n) _q_XMMReg[1 - (n)] +#define XMM_D(n) _d_XMMReg[1 - (n)] #define MMX_B(n) _b_MMXReg[7 - (n)] #define MMX_W(n) _w_MMXReg[3 - (n)] @@ -1279,6 +1302,14 @@ typedef struct BNDCSReg { #define ZMM_S(n) _s_ZMMReg[n] #define ZMM_Q(n) _q_ZMMReg[n] #define ZMM_D(n) _d_ZMMReg[n] +#define ZMM_X(n) _x_ZMMReg[n] + +#define XMM_B(n) _b_XMMReg[n] +#define XMM_W(n) _w_XMMReg[n] +#define XMM_L(n) _l_XMMReg[n] +#define XMM_S(n) _s_XMMReg[n] +#define XMM_Q(n) _q_XMMReg[n] +#define XMM_D(n) _d_XMMReg[n] #define MMX_B(n) _b_MMXReg[n] #define MMX_W(n) _w_MMXReg[n]