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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020adff445000000b0021e5f32ade7sm11725343wrp.68.2022.07.26.11.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 11:23:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [RFC 2/2] hw/ppc/ppc440_uc: Handle mapping failure in DMA engine Date: Tue, 26 Jul 2022 19:23:41 +0100 Message-Id: <20220726182341.1888115-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220726182341.1888115-1-peter.maydell@linaro.org> References: <20220726182341.1888115-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the code for doing DMA in dcr_write_dma() has no fallback code for if its calls to cpu_physical_memory_map() fail. Add handling for this situation, by using address_space_read() and address_space_write() to do the data transfers. Signed-off-by: Peter Maydell --- I believe this to be equivalent to the fastpath code. However, as the comments note, I don't know what the intended behaviour on a DMA memory access error is, because I couldn't find a datasheet for this hardware. I am also a bit suspicious that the current code does not seem to update any of the count, source or destination addresses after the memory transfer: is that really how the hardware behaves? --- hw/ppc/ppc440_uc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 11fdb88c220..0879f180a14 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -905,6 +905,7 @@ static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) uint8_t *rptr, *wptr; hwaddr rlen, wlen; hwaddr xferlen; + bool fastpathed = false; sidx = didx = 0; width = 1 << ((val & DMA0_CR_PW) >> 25); @@ -915,6 +916,7 @@ static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, true); if (rptr && rlen == xferlen && wptr && wlen == xferlen) { + fastpathed = true; if (!(val & DMA0_CR_DEC) && val & DMA0_CR_SAI && val & DMA0_CR_DAI) { /* optimise common case */ @@ -940,6 +942,33 @@ static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) if (rptr) { cpu_physical_memory_unmap(rptr, rlen, 0, sidx); } + if (!fastpathed) { + /* Fast-path failed, do each access one at a time */ + for (sidx = didx = i = 0; i < count; i++) { + uint8_t buf[8]; + assert(width <= sizeof(buf)); + if (address_space_read(&address_space_memory, + dma->ch[chnl].sa + sidx, + MEMTXATTRS_UNSPECIFIED, + buf, width) != MEMTX_OK) { + /* FIXME: model correct behaviour on errors */ + break; + } + if (address_space_write(&address_space_memory, + dma->ch[chnl].da + didx, + MEMTXATTRS_UNSPECIFIED, + buf, width) != MEMTX_OK) { + /* FIXME: model correct behaviour on errors */ + break; + } + if (val & DMA0_CR_SAI) { + sidx += width; + } + if (val & DMA0_CR_DAI) { + didx += width; + } + } + } } } break;