From patchwork Mon Jun 27 10:22:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 585275 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2948347mab; Mon, 27 Jun 2022 03:29:24 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s/cX4/HirWPut9lpXKClaV+0xNgD4aoJo/jCSZQ9noSytK4Qxb8O4lenuBobsUhiL3Jx2c X-Received: by 2002:a37:6656:0:b0:6af:1d6:9aea with SMTP id a83-20020a376656000000b006af01d69aeamr7190067qkc.242.1656325764782; Mon, 27 Jun 2022 03:29:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656325764; cv=none; d=google.com; s=arc-20160816; b=KeY3ywIt8dXXBFD80Dat/YmvTGLqsNH4EWE+hOGlKkuCroe0E+QX87j5zikwBpy1FH lb78R/FZ84kQnqB/5WuVZum0kwyE4ULg4/KK8GrTs39K+r1lUBdUtBgarFKNsvZhLU7j 3ChANz9aV9HAliEXxaUs6m57S/QEndrDX0R0M1D5MLkUTe0e8B+uGMD0MQUbMV0GJTp2 R0C8cVdQH+GTkQ47GHaDwuPQPrMyczdTDvX+sT/VE5EpJm/UI1PIqndDzv90rfI6EobI Wyu+wE5kzTJseiW28xLM7pyzGSIzw8X+6W62sZDCtsCAATWsjG99wcBL0DoWz37Lh0Hy XACg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=n62ubY7+iB/7rTCXmZ/zUPH5zT2IZxj1SHTY5yvBRm8=; b=Ak6bLlPph2086JTgGqeXPZd8bFPoDbK2qwxaXD6e+3PISN9sCCnr+NKmg8Kp8pq1eV D8qLs7mfVdoM0eGpW9OoPEyaKgBlSGvzw3tHcZLMOeegsFVNoMRAZ5aZLKpf0mlkxfb2 4wRhQq6oexshxzQ1oAGdWoMxoANtbHMPuLQSEB0Kzrld25cJpwHR8BJQcGNAjbihSDwz uGL1bA0n6lmBVtaDl5dlVumC+Zz4anX5EUGTpfPKDwfJ8cdOBZY7yo+rOGFnhf6lP3lu KXShq35OG78CQfEetJXjt7VpkdYT4FcZMvlujvNxUZ071ooG0gH3CtegyfRQRbGpVnlF C4uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QxR2jP0R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u11-20020ad45aab000000b004705f52a106si5234240qvg.420.2022.06.27.03.29.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jun 2022 03:29:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QxR2jP0R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5lzg-0008WT-BE for patch@linaro.org; Mon, 27 Jun 2022 06:29:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5ltJ-0002JR-3h for qemu-devel@nongnu.org; Mon, 27 Jun 2022 06:22:49 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:39866) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o5ltD-0004rv-K1 for qemu-devel@nongnu.org; Mon, 27 Jun 2022 06:22:48 -0400 Received: by mail-wr1-x42e.google.com with SMTP id k22so12340593wrd.6 for ; Mon, 27 Jun 2022 03:22:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=n62ubY7+iB/7rTCXmZ/zUPH5zT2IZxj1SHTY5yvBRm8=; b=QxR2jP0RbnY9kNPOLur59/p6YtdZX6h5GZmjUVDzr9DCAPmrUDMNCK3LeAFTf3lWOq Z/oPFdQyNPtHRznDVLVL/YJItlrIBbMDxSpyG7h6n5idQMLqysPugHeSpazMlwtM4f40 CJKjNkF8WJbipUf9X0yMljZZ+Pvlm6FBqQ59vaPLrOIhj+0pXhpi9Q4xrvdk7Obf0hb6 zhKdI40oqgUnL4raENszGAXUdoKFtbIf25Shcpn52MmILoDW3MMqYdc5DU0xxGNKqm3C /Yj+bO1XLLRasaQpv2p57X65iPMedsh09P7tIIxrPx8Nv4cRMqeaA5V14FWZRVzfCRkC CrFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n62ubY7+iB/7rTCXmZ/zUPH5zT2IZxj1SHTY5yvBRm8=; b=3FfzDqxL4JJNNIaxn8GaN0Ws6VFe4mM3sq/N2ai24vUMruNvmkz2T+w4xE0sl49Tip X4NVoxc4wVuOddCjCN8IVae7LQnBZ0JO7gimnot1WbDDCyRW775zafQd/WE9Oko/tddl BD3rVDaxTszoFshDr83ikhOIcVkR3teHOlzdJWeqc55p9BTGkxEtjxPHix2Ty4N27N3i vQDOC6kzkjGxP70K+TY+8Dr+daU50yGo8+pOW6ehw3fQxJp/T4PD1wNFUlvNT7zaCNbo qY/lubljqZxyzMRloJi939AzAtHY/6sON2yl3hbssfIagFBiv1nqlSuBhCrcm7UnfZPJ JiTQ== X-Gm-Message-State: AJIora+1eMkofXyOzLyBZeB+0VQ+IPd72WpCH2hqzsTmfQpqpHr/FVCe xXCJPwxaOL0jGWNLUSEUIxAQu0SPLy2vCQ== X-Received: by 2002:adf:db50:0:b0:21b:8a4c:594b with SMTP id f16-20020adfdb50000000b0021b8a4c594bmr11420005wrj.564.1656325362299; Mon, 27 Jun 2022 03:22:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d11-20020a5d6dcb000000b0020e6ce4dabdsm9754335wrz.103.2022.06.27.03.22.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 03:22:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/25] target/arm: Add SMEEXC_EL to TB flags Date: Mon, 27 Jun 2022 11:22:16 +0100 Message-Id: <20220627102236.3097629-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627102236.3097629-1-peter.maydell@linaro.org> References: <20220627102236.3097629-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This is CheckSMEAccess, which is the basis for a set of related tests for various SME cpregs and instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220620175235.60881-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c | 52 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 56 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05d1e2e8dd1..e99de180978 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1134,6 +1134,7 @@ void aarch64_sync_64_to_32(CPUARMState *env); int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); +int sme_exception_el(CPUARMState *env, int cur_el); /** * sve_vqm1_for_el: @@ -3148,6 +3149,7 @@ FIELD(TBFLAG_A64, ATA, 15, 1) FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) +FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index 88dc18a034b..c88c9533253 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -42,6 +42,7 @@ typedef struct DisasContext { bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ + int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; diff --git a/target/arm/helper.c b/target/arm/helper.c index d21ba7ab836..2c080c6cac0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6218,6 +6218,55 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } +/* + * Return the exception level to which exceptions should be taken for SME. + * C.f. the ARM pseudocode function CheckSMEAccess. + */ +int sme_exception_el(CPUARMState *env, int el) +{ +#ifndef CONFIG_USER_ONLY + if (el <= 1 && !el_is_in_host(env, el)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { + case 1: + if (el != 0) { + break; + } + /* fall through */ + case 0: + case 2: + return 1; + } + } + + if (el <= 2 && arm_is_el2_enabled(env)) { + /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ + if (env->cp15.hcr_el2 & HCR_E2H) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { + case 1: + if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { + break; + } + /* fall through */ + case 0: + case 2: + return 2; + } + } else { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { + return 2; + } + } + } + + /* CPTR_EL3. Since ESM is negative we must check for EL3. */ + if (arm_feature(env, ARM_FEATURE_EL3) + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { + return 3; + } +#endif + return 0; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -11197,6 +11246,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + } sctlr = regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4c64546090c..9a285dd1774 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14603,6 +14603,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); + dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT);