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([2602:47:d49e:3c01:a3e0:8a80:7b85:aea6]) by smtp.gmail.com with ESMTPSA id q11-20020a056a00084b00b0051bc3a2355csm9907875pfk.64.2022.06.20.18.48.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 18:48:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: npiggin@gmail.com, qemu-ppc@nongnu.org Subject: [PATCH v2 2/3] util/cacheflush: Merge aarch64 ctr_el0 usage Date: Mon, 20 Jun 2022 18:48:36 -0700 Message-Id: <20220621014837.189139-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220621014837.189139-1-richard.henderson@linaro.org> References: <20220621014837.189139-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Merge init_ctr_el0 into arch_cache_info. In flush_idcache_range, use the pre-computed line sizes from the global variables. Use CONFIG_DARWIN in preference to __APPLE__. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- util/cacheflush.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/util/cacheflush.c b/util/cacheflush.c index 8096afd33c..01b6cb7583 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -70,7 +70,7 @@ static void sys_cache_info(int *isize, int *dsize) g_free(buf); } -#elif defined(__APPLE__) +#elif defined(CONFIG_DARWIN) # include static void sys_cache_info(int *isize, int *dsize) { @@ -117,20 +117,25 @@ static void sys_cache_info(int *isize, int *dsize) * Architecture (+ OS) specific cache detection mechanisms. */ -#if defined(__aarch64__) - +#if defined(__aarch64__) && !defined(CONFIG_DARWIN) +/* Apple does not expose CTR_EL0, so we must use system interfaces. */ +static uint64_t save_ctr_el0; static void arch_cache_info(int *isize, int *dsize) { - if (*isize == 0 || *dsize == 0) { - uint64_t ctr; + uint64_t ctr; - /* - * The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, - * but (at least under Linux) these are marked protected by the - * kernel. However, CTR_EL0 contains the minimum linesize in the - * entire hierarchy, and is used by userspace cache flushing. - */ - asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); + /* + * The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, + * but (at least under Linux) these are marked protected by the + * kernel. However, CTR_EL0 contains the minimum linesize in the + * entire hierarchy, and is used by userspace cache flushing. + * + * We will also use this value in flush_idcache_range. + */ + asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); + save_ctr_el0 = ctr; + + if (*isize == 0 || *dsize == 0) { if (*isize == 0) { *isize = 4 << (ctr & 0xf); } @@ -228,17 +233,6 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) } #else -/* - * TODO: unify this with cacheinfo.c. - * We want to save the whole contents of CTR_EL0, so that we - * have more than the linesize, but also IDC and DIC. - */ -static uint64_t save_ctr_el0; -static void __attribute__((constructor)) init_ctr_el0(void) -{ - asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); -} - /* * This is a copy of gcc's __aarch64_sync_cache_range, modified * to fit this three-operand interface. @@ -248,8 +242,8 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) const unsigned CTR_IDC = 1u << 28; const unsigned CTR_DIC = 1u << 29; const uint64_t ctr_el0 = save_ctr_el0; - const uintptr_t icache_lsize = 4 << extract64(ctr_el0, 0, 4); - const uintptr_t dcache_lsize = 4 << extract64(ctr_el0, 16, 4); + const uintptr_t icache_lsize = qemu_icache_linesize; + const uintptr_t dcache_lsize = qemu_dcache_linesize; uintptr_t p; /*