From patchwork Thu Jun 9 09:05:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580245 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp600500max; Thu, 9 Jun 2022 02:28:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwXzqKAn60iXXkeTsjjNRTKnEb3KGT3TXME0We9i4MtRXQtd9MssVH7s5MZlZyzVFv2Fk6k X-Received: by 2002:a05:6214:62f:b0:468:1689:a1d8 with SMTP id a15-20020a056214062f00b004681689a1d8mr23305341qvx.0.1654766891028; Thu, 09 Jun 2022 02:28:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766891; cv=none; d=google.com; s=arc-20160816; b=OJUJTbYmn2E7pcomSxfozDNYoDW6rBPUTIYyCwnlW2l+nqW11WH+L1i6tkK76YgUTN i1up5f5uBUKAAJzmJ4faImSBJHxU/1NOhbRACtDvNfqFT1ExRSRu/Oo2Rmb9KFeqh+Z7 ssQqW9Gx1TuTr6PKC5G/BnX5XtAqVGFozOxGT39QLjaeMRjjFkvQMW5dEQLiwguBgGWK xScTmiL3RVfIlEznOV9aGazKUyYzTqZDnew5Md7McR9RRSwW5IAli4Re9bK1L3K4vnrZ OJsVyeXthmba5Ag5WxEq10rbgVzJ+fY/8kkq+DjYJ7p2m0pa2oLTxdSfIp/osc79O9Qc Eepg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NDy5L1j1NFeCwxkRreoifiteCmt9uSlmxDgPX55fTNU=; b=W/TLhT+ZhB3NKhq26OWl2AXmN1OPvlvsKPKxAHwpRYoiFv8ZVCPo9qRFfLNURGYz2P 1qj8sWoUb/K/C4nRjjCSj7AR7pcpEv7UPJGMwQnOJGpAmblRnN0WDKJtXFE76UkUN5wN VUngfWlPtdmrem5KwxxrbvWXSgh+c8j6W/RPKbrdir3NiBD5mTd47ob1ILbWNhp/Ck1C 4rAPt7wLeys5TrJDnwc2LO5Jg3GDki4AjKN4s//c/LzOpQdM1iagaXU8cMxIxBuT3h6J ljG1ojXuLMM5gVyPi0Y9svL+rOwXdxHRNczI3lmw59ULbAe7ECoimnoBWGiOPMk3kxqj 5N/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rn1tLAMC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j2-20020ae9c202000000b006a57b09338asi7525713qkg.726.2022.06.09.02.28.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:28:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rn1tLAMC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzESW-00068f-HN for patch@linaro.org; Thu, 09 Jun 2022 05:28:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7O-0001Z0-C6 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:33709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7J-00063a-3z for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:16 -0400 Received: by mail-wr1-x433.google.com with SMTP id h5so31518410wrb.0 for ; Thu, 09 Jun 2022 02:06:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NDy5L1j1NFeCwxkRreoifiteCmt9uSlmxDgPX55fTNU=; b=rn1tLAMCWtRlYx+ukNHwDCZj515mfgswJ40a7U18/L+lO0lftUle6LtLJeyoL/RR0U RD6fk/Zm9bLDbnBO0SJrf4oNqdRMTWGVuqPjxxWUDrXcf18+rGC76tauOmVJ9qoxL/z+ NJozbTPGz3tExs0djCv+dhNvWukoUPtLIaYGqaG3g85gqbV8ITy3roqwoKTO/axTWtM4 1v3+j1zlAo0EZbXcgWmtPpG3mZ1fAwvb94GZj3fdFF/Pw66G0yQWV6rX8NxIsCCMBGXc x7KzeEnGwSJR0cCmw1TDKcrZd2Wyv/Sz79GkKx6DFIhAjX/CLJ18Taz4eXwCG+2KfLVF mwVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NDy5L1j1NFeCwxkRreoifiteCmt9uSlmxDgPX55fTNU=; b=WhLQMpp7OIQHBXsMowJqVTSIO7QcY5dx+I+GuW+lwEEnIeTXHcnqab4J5AP4GaI932 7S2iXKOlbBn59uyFs40KAqWZAU2MjIRDY7hd0Lb1eN9iZYxJGFU5EA+Dkh5hxWR3meoj R6EhNqaAF2atUNBJmpCJKuVBzyPKczlvM520bqKWkWVcNu0fj+mJ44ZfwcHgfybkM7i3 oaQxm/+zW5gAK9qH8lEQ+Ov/q3e16Ya+bAAbtjK/Hol5NuarvSS1kwybzCS1IpSI4BGL YC9XCiB7KZj2DtxtYkwqULB1sjAi8wpj+5/TPpogKVK57OBVngj9v1FcYh4LFaBob2r1 SodQ== X-Gm-Message-State: AOAM532dr2dVZwx7VrKHUczcnH8slD8ALASykhDSD/wiSom4VY6K/yku qkLPUThqEqUDCl1Fjbv+LkYMKlee3jUhhg== X-Received: by 2002:adf:eccd:0:b0:212:fbbc:79de with SMTP id s13-20020adfeccd000000b00212fbbc79demr35774935wro.520.1654765571489; Thu, 09 Jun 2022 02:06:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/55] target/arm: Move aa32_va_parameters to ptw.c Date: Thu, 9 Jun 2022 10:05:10 +0100 Message-Id: <20220609090537.1971756-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-22-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 3 --- target/arm/helper.c | 64 --------------------------------------------- target/arm/ptw.c | 64 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 67 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index a71161b01bd..9314fb4d23c 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -25,8 +25,5 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } -ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, - ARMMMUIdx mmu_idx); - #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2526f4c6c4a..f61f1da61e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10771,70 +10771,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } #ifndef CONFIG_USER_ONLY -ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, - ARMMMUIdx mmu_idx) -{ - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - uint32_t el = regime_el(env, mmu_idx); - int select, tsz; - bool epd, hpd; - - assert(mmu_idx != ARMMMUIdx_Stage2_S); - - if (mmu_idx == ARMMMUIdx_Stage2) { - /* VTCR */ - bool sext = extract32(tcr, 4, 1); - bool sign = extract32(tcr, 3, 1); - - /* - * If the sign-extend bit is not the same as t0sz[3], the result - * is unpredictable. Flag this as a guest error. - */ - if (sign != sext) { - qemu_log_mask(LOG_GUEST_ERROR, - "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); - } - tsz = sextract32(tcr, 0, 4) + 8; - select = 0; - hpd = false; - epd = false; - } else if (el == 2) { - /* HTCR */ - tsz = extract32(tcr, 0, 3); - select = 0; - hpd = extract64(tcr, 24, 1); - epd = false; - } else { - int t0sz = extract32(tcr, 0, 3); - int t1sz = extract32(tcr, 16, 3); - - if (t1sz == 0) { - select = va > (0xffffffffu >> t0sz); - } else { - /* Note that we will detect errors later. */ - select = va >= ~(0xffffffffu >> t1sz); - } - if (!select) { - tsz = t0sz; - epd = extract32(tcr, 7, 1); - hpd = extract64(tcr, 41, 1); - } else { - tsz = t1sz; - epd = extract32(tcr, 23, 1); - hpd = extract64(tcr, 42, 1); - } - /* For aarch32, hpd0 is not enabled without t2e as well. */ - hpd &= extract32(tcr, 6, 1); - } - - return (ARMVAParameters) { - .tsz = tsz, - .select = select, - .epd = epd, - .hpd = hpd, - }; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 525272e99af..427813ea563 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -615,6 +615,70 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } +static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el = regime_el(env, mmu_idx); + int select, tsz; + bool epd, hpd; + + assert(mmu_idx != ARMMMUIdx_Stage2_S); + + if (mmu_idx == ARMMMUIdx_Stage2) { + /* VTCR */ + bool sext = extract32(tcr, 4, 1); + bool sign = extract32(tcr, 3, 1); + + /* + * If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. + */ + if (sign != sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); + } + tsz = sextract32(tcr, 0, 4) + 8; + select = 0; + hpd = false; + epd = false; + } else if (el == 2) { + /* HTCR */ + tsz = extract32(tcr, 0, 3); + select = 0; + hpd = extract64(tcr, 24, 1); + epd = false; + } else { + int t0sz = extract32(tcr, 0, 3); + int t1sz = extract32(tcr, 16, 3); + + if (t1sz == 0) { + select = va > (0xffffffffu >> t0sz); + } else { + /* Note that we will detect errors later. */ + select = va >= ~(0xffffffffu >> t1sz); + } + if (!select) { + tsz = t0sz; + epd = extract32(tcr, 7, 1); + hpd = extract64(tcr, 41, 1); + } else { + tsz = t1sz; + epd = extract32(tcr, 23, 1); + hpd = extract64(tcr, 42, 1); + } + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &= extract32(tcr, 6, 1); + } + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .epd = epd, + .hpd = hpd, + }; +} + /* * check_s2_mmu_setup * @cpu: ARMCPU