@@ -1251,8 +1251,9 @@ enum {
EXCP_MSAFPE,
EXCP_TLBXI,
EXCP_TLBRI,
+ EXCP_SEMIHOST,
- EXCP_LAST = EXCP_TLBRI,
+ EXCP_LAST = EXCP_SEMIHOST,
};
/*
@@ -62,6 +62,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void mips_semihosting(CPUMIPSState *env);
+
#endif /* !CONFIG_USER_ONLY */
#endif
@@ -9,8 +9,6 @@
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
-DEF_HELPER_1(do_semihosting, void, env)
-
/* CP0 helpers */
DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
DEF_HELPER_1(mfc0_mvpconf0, tl, env)
@@ -125,6 +125,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_TLBRI] = "TLB read-inhibit",
[EXCP_MSADIS] = "MSA disabled",
[EXCP_MSAFPE] = "MSA floating point",
+ [EXCP_SEMIHOST] = "Semihosting",
};
const char *mips_exception_name(int32_t exception)
@@ -20,10 +20,10 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/log.h"
-#include "exec/helper-proto.h"
#include "semihosting/softmmu-uaccess.h"
#include "semihosting/semihost.h"
#include "semihosting/console.h"
+#include "internal.h"
typedef enum UHIOp {
UHI_exit = 1,
@@ -238,7 +238,7 @@ static int copy_argn_to_target(CPUMIPSState *env, int arg_num,
unlock_user(p, gpr, 0); \
} while (0)
-void helper_do_semihosting(CPUMIPSState *env)
+void mips_semihosting(CPUMIPSState *env)
{
target_ulong *gpr = env->active_tc.gpr;
const UHIOp op = gpr[25];
@@ -1053,6 +1053,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
}
offset = 0x180;
switch (cs->exception_index) {
+ case EXCP_SEMIHOST:
+ cs->exception_index = EXCP_NONE;
+ mips_semihosting(env);
+ return;
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
/*
@@ -12094,14 +12094,6 @@ static inline bool is_uhi(int sdbbp_code)
#endif
}
-#ifdef CONFIG_USER_ONLY
-/* The above should dead-code away any calls to this..*/
-static inline void gen_helper_do_semihosting(void *env)
-{
- g_assert_not_reached();
-}
-#endif
-
void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
{
TCGv t0 = tcg_temp_new();
@@ -13910,7 +13902,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
break;
case R6_OPC_SDBBP:
if (is_uhi(extract32(ctx->opcode, 6, 20))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
gen_reserved_instruction(ctx);
@@ -14322,7 +14314,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SDBBP:
if (is_uhi(extract32(ctx->opcode, 6, 20))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
/*
* XXX: not clear which exception should be raised
@@ -826,7 +826,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
break;
case SDBBP16:
if (is_uhi(extract32(ctx->opcode, 0, 4))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
/*
* XXX: not clear which exception should be raised
@@ -942,7 +942,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
case R6_SDBBP16:
/* SDBBP16 */
if (is_uhi(extract32(ctx->opcode, 6, 4))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
generate_exception(ctx, EXCP_RI);
@@ -1311,7 +1311,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
break;
case SDBBP:
if (is_uhi(extract32(ctx->opcode, 16, 10))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
check_insn(ctx, ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_SBRI) {
@@ -952,7 +952,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
break;
case RR_SDBBP:
if (is_uhi(extract32(ctx->opcode, 5, 6))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
/*
* XXX: not clear which exception should be raised
@@ -3691,7 +3691,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SDBBP:
if (is_uhi(extract32(ctx->opcode, 0, 19))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
gen_reserved_instruction(ctx);
@@ -4609,7 +4609,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SDBBP16:
if (is_uhi(extract32(ctx->opcode, 0, 3))) {
- gen_helper_do_semihosting(cpu_env);
+ generate_exception_end(ctx, EXCP_SEMIHOST);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
gen_reserved_instruction(ctx);
Within do_interrupt, we hold the iothread lock, which is required for Chardev access for the console, and for the round trip for use_gdb_syscalls(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/mips/cpu.h | 3 ++- target/mips/tcg/tcg-internal.h | 2 ++ target/mips/tcg/sysemu_helper.h.inc | 2 -- target/mips/tcg/exception.c | 1 + target/mips/tcg/sysemu/mips-semi.c | 4 ++-- target/mips/tcg/sysemu/tlb_helper.c | 4 ++++ target/mips/tcg/translate.c | 12 ++---------- target/mips/tcg/micromips_translate.c.inc | 6 +++--- target/mips/tcg/mips16e_translate.c.inc | 2 +- target/mips/tcg/nanomips_translate.c.inc | 4 ++-- 10 files changed, 19 insertions(+), 21 deletions(-)