From patchwork Tue Jun 7 20:32:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579349 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp5510083max; Tue, 7 Jun 2022 14:04:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyI5C9IGZw2XBXKIOy2/rycAInp3H2j9Htvu5nuinSaRRbRDPXFiIjkeS52Diz41prBqkri X-Received: by 2002:a37:a584:0:b0:6a6:8fd2:fd4b with SMTP id o126-20020a37a584000000b006a68fd2fd4bmr17947605qke.734.1654635887530; Tue, 07 Jun 2022 14:04:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654635887; cv=none; d=google.com; s=arc-20160816; b=BEJtBZce/SUklrskZAW1DFBid7CcS0oVmExEse6tkt2911+0JOoYQHxGlUwaEVbHmG b+iLK0txQl1VtooUdiCm9d0MGWeRqYdfAERI7Dwek19eLtQ7yMPO3TSED0VMVP/TS57/ DcvjtRCyT6mfzUt5fRqIULZ1bfaOX1kys26FeO2he9zcLbieisP7OCiQFIQJG8U2Ulh2 rb+V3zlH9lucgae1fCugGDLSaJ0TonvNwgc9yKshAVNUkwLEcwakt/lcaDFHIUu1Z9B6 t8JaES6hAkgPBcPwpZdQxN5aHuY7fddHGO72xBs0lZiRF01yAX1pQZ3SRNmVPiKp7u7F ckYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/BExpvNtfeOaLygKWpS4gykSxDaWFRszDLVZHG0ddOs=; b=rNNcJPW3dPflp1Md1XcdVOuEA8KjyxOBHW1MJwHb9eQ7eh4vIhaf+NzHXqkKjBJW6N nVpT5IX8Jy+Lsep4hE1pMJiWEkvnhx3pR0UT2FCU3eloZWtNgSQqnvCQ8x+L3QFcz4jH UYnRyYcyQflifXwpEFj7qHqanaAzXMNt8Pm/cHI4MP5U0l34DitJjzIFpz2sPFMxGJyN mLQ3lqmnYnQd2MNhjHjsO83I5p2gQ08+xfm5J2xKiLFGX6JTLsJi4VWcxyREKwVN9V4/ C5tg3XrYvogmb23vzOh+VpBzCvX8bKLGMTEALS8/421B4+yRzWjthXWaclwx6mFy4C4t S1+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rJGZ3JN4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i6-20020a05620a27c600b006a6aefe6320si5425838qkp.716.2022.06.07.14.04.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Jun 2022 14:04:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rJGZ3JN4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygNb-0007GZ-2J for patch@linaro.org; Tue, 07 Jun 2022 17:04:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftg-0000TN-2j for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:52 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:33553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftY-0007UU-Rn for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:51 -0400 Received: by mail-pl1-x62f.google.com with SMTP id f9so5339584plg.0 for ; Tue, 07 Jun 2022 13:33:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/BExpvNtfeOaLygKWpS4gykSxDaWFRszDLVZHG0ddOs=; b=rJGZ3JN4OKBU1KQw89iQN+g+iPge1iOVfJsVnWT21IFxVLebZ/EGUO/fOD6Q1Snl1v d1LqkT9atDKjvLT65sQQB7qObN1hGyFKGvzA69t6DOCemPan1SkgQQxdnWs9AF30NFUu QF0vU0W06M3z2nuyu0dWzqzwMS3y4ruTV+fYbtB1tbhvDLEYr3cKVpaVOfJs15Re1ISW WhC53+BKUvgbD6+biN91cI0odEHYH510pB4s5GDdzrA4vhMD7xx2BhwT+pdEbBc/HYS+ iOgyqZt0btkbXwNHfcZVBvzFxwbn3bFPfQzAE7/jd63A51JD++2rH2jSoJ7SNRVOEfU1 mFlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/BExpvNtfeOaLygKWpS4gykSxDaWFRszDLVZHG0ddOs=; b=AhL/613ZUy2PoclmeI1q6a8tuG6w7uaV+OOdn7jQqrtEu2cVw3+wg5ic5jXhowAlu2 Jv6cuBPnQ4YjHh6l5VxJRmVekKMOJwmxt+mZn91GrOmfmQWt9jqZiUz9vaBWD+01k+KS jwo+iYUZSElrWuMMSLs7XiUz1EhFzjeIQQLGik45rwMnk6yxs7rHZG/IGbqsC9xBEMQ6 D6SMZro4nJ1kntInTeI42HWfwj0srGcDdeai3sJ7djQM7DjK2nrIujTm0nJg/Ykovw9R 0g4FnHZv2W1/yp9Zdz8P0giUy+6jug5TvZGTCJoq2IE2kDVkdpk5ByaUu7MdFAO5J1J0 uVjg== X-Gm-Message-State: AOAM533YbrwvYzcw5IsWWLWr0FrKzifjkUnZH3381gSGeTflJyV+vrPA TZYdk2E0fSQ8BJ+xYeajI0NMA2Ytpw3eAw== X-Received: by 2002:a17:90a:df16:b0:1e3:1cd:6c6f with SMTP id gp22-20020a17090adf1600b001e301cd6c6fmr50299220pjb.10.1654634023471; Tue, 07 Jun 2022 13:33:43 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 39/71] target/arm: Add SVL to TB flags Date: Tue, 7 Jun 2022 13:32:34 -0700 Message-Id: <20220607203306.657998-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need SVL separate from VL for RDSVL at al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ target/arm/translate.h | 1 + target/arm/helper.c | 8 +++++++- target/arm/translate-a64.c | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d7d364abbb..23d46c7d7d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) +FIELD(TBFLAG_A64, SVL, 24, 4) /* * Helpers for using the above. @@ -3337,6 +3338,17 @@ static inline int sve_vq(CPUARMState *env) return EX_TBFLAG_A64(env->hflags, VL) + 1; } +/** + * sme_vq + * @env: the cpu context + * + * Return the SVL cached within env->hflags, in units of quadwords. + */ +static inline int sme_vq(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, SVL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/target/arm/translate.h b/target/arm/translate.h index fbd6713572..1330281f8b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -44,6 +44,7 @@ typedef struct DisasContext { int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ + int svl; /* current streaming vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3. */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b1ca819597..2b38e82c22 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13874,7 +13874,13 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + int sme_el = sme_exception_el(env, el); + + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); + if (sme_el == 0) { + /* Similarly, do not compute SVL if SME is disabled. */ + DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 40f2e53983..b1d2840819 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14652,6 +14652,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; + dc->svl = (EX_TBFLAG_A64(tb_flags, SVL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE);