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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 24/25] target/arm: Rearrange Secure PL1 test in arm_debug_target_el Date: Mon, 6 Jun 2022 19:47:33 -0700 Message-Id: <20220607024734.541321-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not a bug, because arm_is_el2_enabled tests for secure, and SCR_EL3.EEL2 cannot be set for AArch32, however the ordering of the tests looks odd. Mirror the structure over in exception_target_el(). Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/debug_helper.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b18a6bd3a2..59dfcb5d5c 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -15,22 +15,24 @@ /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { - bool secure = arm_is_secure(env); - bool route_to_el2 = false; - - if (arm_is_el2_enabled(env)) { - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { + /* + * No such thing as secure EL1 if EL3 is AArch32. + * Remap Secure PL1 to EL3. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { return 3; - } else { - return 1; } + + /* + * HCR.TGE redirects EL0 exceptions from EL1 to EL2. + * MDCR.TDE redirects both EL0 and EL1 debug exceptions to EL2. + */ + if (arm_is_el2_enabled(env) && + (env->cp15.hcr_el2 & HCR_TGE || env->cp15.mdcr_el2 & MDCR_TDE)) { + return 2; + } + + return 1; } /*