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([2602:ae:1547:e101:dd1c:9738:3e40:ffe0]) by smtp.gmail.com with ESMTPSA id z14-20020a17090a170e00b001df239bab14sm10667754pjd.46.2022.06.06.16.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 16:18:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =gaosong@loongson.cn, yangxiaojuan@loongson.cn, Song Gao Subject: [PULL 41/43] target/loongarch: Add gdb support. Date: Mon, 6 Jun 2022 16:14:48 -0700 Message-Id: <20220606231450.448443-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220606231450.448443-1-richard.henderson@linaro.org> References: <20220606231450.448443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Xiaojuan Yang Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-Id: <20220606124333.2060567-42-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson --- configs/targets/loongarch64-softmmu.mak | 1 + target/loongarch/internals.h | 4 ++ target/loongarch/cpu.c | 9 +++ target/loongarch/gdbstub.c | 81 +++++++++++++++++++++++++ MAINTAINERS | 1 + gdb-xml/loongarch-base64.xml | 44 ++++++++++++++ gdb-xml/loongarch-fpu64.xml | 57 +++++++++++++++++ target/loongarch/meson.build | 1 + 8 files changed, 198 insertions(+) create mode 100644 target/loongarch/gdbstub.c create mode 100644 gdb-xml/loongarch-base64.xml create mode 100644 gdb-xml/loongarch-fpu64.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index 666154022f..7bc06c850c 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=loongarch64 TARGET_BASE_ARCH=loongarch TARGET_SUPPORTS_MTTCG=y +TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index a410c41c37..9d50fbdd81 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -49,4 +49,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n); +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs); + #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 3b7d6289d2..4c8f96bc3a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -487,6 +487,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) return; } + loongarch_cpu_register_gdb_regs_for_features(cs); + cpu_reset(cs); qemu_init_vcpu(cs); @@ -640,6 +642,13 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) dc->vmsd = &vmstate_loongarch_cpu; cc->sysemu_ops = &loongarch_sysemu_ops; cc->disas_set_info = loongarch_cpu_disas_set_info; + cc->gdb_read_register = loongarch_cpu_gdb_read_register; + cc->gdb_write_register = loongarch_cpu_gdb_write_register; + cc->disas_set_info = loongarch_cpu_disas_set_info; + cc->gdb_num_core_regs = 34; + cc->gdb_core_xml_file = "loongarch-base64.xml"; + cc->gdb_stop_before_watchpoint = true; + #ifdef CONFIG_TCG cc->tcg_ops = &loongarch_tcg_ops; #endif diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c new file mode 100644 index 0000000000..0c48834201 --- /dev/null +++ b/target/loongarch/gdbstub.c @@ -0,0 +1,81 @@ +/* + * LOONGARCH gdb server stub + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/gdbstub.h" + +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + + if (0 <= n && n < 32) { + return gdb_get_regl(mem_buf, env->gpr[n]); + } else if (n == 32) { + return gdb_get_regl(mem_buf, env->pc); + } else if (n == 33) { + return gdb_get_regl(mem_buf, env->badaddr); + } + return 0; +} + +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + target_ulong tmp = ldtul_p(mem_buf); + int length = 0; + + if (0 <= n && n < 32) { + env->gpr[n] = tmp; + length = sizeof(target_ulong); + } else if (n == 32) { + env->pc = tmp; + length = sizeof(target_ulong); + } + return length; +} + +static int loongarch_gdb_get_fpu(CPULoongArchState *env, + GByteArray *mem_buf, int n) +{ + if (0 <= n && n < 32) { + return gdb_get_reg64(mem_buf, env->fpr[n]); + } else if (32 <= n && n < 40) { + return gdb_get_reg8(mem_buf, env->cf[n - 32]); + } else if (n == 40) { + return gdb_get_reg32(mem_buf, env->fcsr0); + } + return 0; +} + +static int loongarch_gdb_set_fpu(CPULoongArchState *env, + uint8_t *mem_buf, int n) +{ + int length = 0; + + if (0 <= n && n < 32) { + env->fpr[n] = ldq_p(mem_buf); + length = 8; + } else if (32 <= n && n < 40) { + env->cf[n - 32] = ldub_p(mem_buf); + length = 1; + } else if (n == 40) { + env->fcsr0 = ldl_p(mem_buf); + length = 4; + } + return length; +} + +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) +{ + gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu, + 41, "loongarch-fpu64.xml", 0); +} diff --git a/MAINTAINERS b/MAINTAINERS index e8938db694..954fb95218 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1137,6 +1137,7 @@ F: include/hw/intc/loongarch_*.h F: hw/intc/loongarch_*.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c +F: gdb-xml/loongarch*.xml M68K Machines ------------- diff --git a/gdb-xml/loongarch-base64.xml b/gdb-xml/loongarch-base64.xml new file mode 100644 index 0000000000..4962bdbd28 --- /dev/null +++ b/gdb-xml/loongarch-base64.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/loongarch-fpu64.xml b/gdb-xml/loongarch-fpu64.xml new file mode 100644 index 0000000000..e52cf89fbc --- /dev/null +++ b/gdb-xml/loongarch-fpu64.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build index 74e5f3b2a7..6376f9e84b 100644 --- a/target/loongarch/meson.build +++ b/target/loongarch/meson.build @@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files( 'fpu_helper.c', 'op_helper.c', 'translate.c', + 'gdbstub.c', )) loongarch_tcg_ss.add(zlib)