diff mbox series

[PULL,36/43] Enable common virtio pci support for LoongArch

Message ID	20220606231450.448443-37-richard.henderson@linaro.org
State	Accepted
Commit	256309e1884898a9cedb44abab0f15c4843e06f6
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: =gaosong@loongson.cn, yangxiaojuan@loongson.cn, Song Gao <gaosong@loongson.cn> Subject: [PULL 36/43] Enable common virtio pci support for LoongArch Date: Mon, 6 Jun 2022 16:14:43 -0700 Message-Id: <20220606231450.448443-37-richard.henderson@linaro.org> In-Reply-To: <20220606231450.448443-1-richard.henderson@linaro.org> References: <20220606231450.448443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	[PULL,01/43] target/loongarch: Add README \| expand [PULL,01/43] target/loongarch: Add README [PULL,02/43] target/loongarch: Add core definition [PULL,03/43] target/loongarch: Add main translation routines [PULL,04/43] target/loongarch: Add fixed point arithmetic instruction translation [PULL,05/43] target/loongarch: Add fixed point shift instruction translation [PULL,06/43] target/loongarch: Add fixed point bit instruction translation [PULL,07/43] target/loongarch: Add fixed point load/store instruction translation [PULL,08/43] target/loongarch: Add fixed point atomic instruction translation [PULL,09/43] target/loongarch: Add fixed point extra instruction translation [PULL,10/43] target/loongarch: Add floating point arithmetic instruction translation [PULL,11/43] target/loongarch: Add floating point comparison instruction translation [PULL,12/43] target/loongarch: Add floating point conversion instruction translation [PULL,13/43] target/loongarch: Add floating point move instruction translation [PULL,14/43] target/loongarch: Add floating point load/store instruction translation [PULL,15/43] target/loongarch: Add branch instruction translation [PULL,16/43] target/loongarch: Add disassembler [PULL,17/43] target/loongarch: Add target build suport [PULL,18/43] target/loongarch: Add system emulation introduction [PULL,19/43] target/loongarch: Add CSRs definition [PULL,20/43] target/loongarch: Add basic vmstate description of CPU. [PULL,21/43] target/loongarch: Implement qmp_query_cpu_definitions() [PULL,22/43] target/loongarch: Add MMU support for LoongArch CPU. [PULL,23/43] target/loongarch: Add LoongArch interrupt and exception handle [PULL,24/43] target/loongarch: Add constant timer support [PULL,25/43] target/loongarch: Add LoongArch CSR instruction [PULL,26/43] target/loongarch: Add LoongArch IOCSR instruction [PULL,27/43] target/loongarch: Add TLB instruction support [PULL,28/43] target/loongarch: Add other core instructions support [PULL,29/43] target/loongarch: Add timer related instructions support. [PULL,30/43] hw/loongarch: Add support loongson3 virt machine type. [PULL,31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) [PULL,32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) [PULL,33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) [PULL,34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) [PULL,35/43] hw/loongarch: Add irq hierarchy for the system [PULL,36/43] Enable common virtio pci support for LoongArch [PULL,37/43] hw/loongarch: Add some devices support for 3A5000. [PULL,38/43] hw/loongarch: Add LoongArch ls7a rtc device support [PULL,39/43] hw/loongarch: Add LoongArch load elf function. [PULL,40/43] hw/loongarch: Add LoongArch virt power manager support. [PULL,41/43] target/loongarch: Add gdb support. [PULL,42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system [PULL,43/43] target/loongarch: 'make check-tcg' support

Commit Message

Richard Henderson June 6, 2022, 11:14 p.m. UTC

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-37-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 softmmu/qdev-monitor.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c
index 12fe60c467..bb5897fc76 100644
--- a/softmmu/qdev-monitor.c
+++ b/softmmu/qdev-monitor.c
@@ -60,7 +60,8 @@  typedef struct QDevAlias
                               QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \
                               QEMU_ARCH_MIPS | QEMU_ARCH_PPC |  \
                               QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \
-                              QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA)
+                              QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA | \
+                              QEMU_ARCH_LOONGARCH)
 #define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)
 #define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)