From patchwork Mon Jun 6 23:14:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578943 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:0:0:0:0 with SMTP id o6csp3056393wru; Mon, 6 Jun 2022 16:21:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0KpekqLYZaRPmIjUUHDyyTyU+8La4B+L/tBlPUiCdxEzBtNALNZzFs0xHDMrx0iiUaUX9 X-Received: by 2002:a05:620a:2804:b0:6a6:781d:434a with SMTP id f4-20020a05620a280400b006a6781d434amr16413230qkp.243.1654557563886; Mon, 06 Jun 2022 16:19:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654557563; cv=none; d=google.com; s=arc-20160816; b=OhoGiK/hq4ZRLxlutyPFzU7pyoEK6vQOpCxWbX1N6fpizriwtAB+74wBKVGekqARex btS5hj6JZt0HxF0Sl2uh2DBoWFdXfMtQ6SmSqsiNvJTVdNdW4YBfeuL/077mTHj8CGgQ Su3UucivkqAUWzgOhY8cWRXjdftMj2546xuGRsBrOF0y73lR+4Cp/nm6s/qQ0l3Zrwhl CZDTM6k6Y0os7KWi/2EFhCyYIQaG6rCDHja/iFJbzlLj10UmZeSNaz5zApzwcsSOHK1X /ZzT5YHmIOq69Iov4lEuxx9czqFinlzjc7ghw0kq90LEu3FgNzUT6fNm6b87uSmohzzT iO0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gNwHQp+abnGkbVRbVu1pbGFEEh9vqf8MUlQTWlzs6xU=; b=Zn/bzemsChtXDeqwvRRUEUsZuNhvszQFTkQ64oAlUA3SZA9Iz6IN5qEV1jjTrEWh+S ue+KJH77GpVOAjCPmNsE2/fpda5/pSw3Ke84abcLikkq/PlmkVUnXa9l0APwKDy1w7bb 461BnlmBS/6TgaPJg5inTttUakM63O+AMGP4fBph9uEY0yCyoRlefWoiaXLdP29OQ+Wm AU2dMAa+yoyEG0E5UKDcY8GwwYS6z7FicZrkx/prTzQg3Z7F30EjIfg6cCyks+9hYbOC BEKLwKPgOBp49IMCRNqUMOKLJ/g72ERRw0/O8DZ9bFKogdlP78J25GI9w5K2/cWchyUl B4SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q65ZwXGd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g8-20020a0562141cc800b00467538eebabsi7824550qvd.547.2022.06.06.16.19.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Jun 2022 16:19:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q65ZwXGd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyM0B-0007jR-Dl for patch@linaro.org; Mon, 06 Jun 2022 19:19:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyLw8-0001W3-Ss for qemu-devel@nongnu.org; Mon, 06 Jun 2022 19:15:05 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:52063) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyLw7-0003l4-18 for qemu-devel@nongnu.org; Mon, 06 Jun 2022 19:15:04 -0400 Received: by mail-pj1-x1035.google.com with SMTP id cx11so14086318pjb.1 for ; Mon, 06 Jun 2022 16:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gNwHQp+abnGkbVRbVu1pbGFEEh9vqf8MUlQTWlzs6xU=; b=Q65ZwXGd95QWinMFgQkNT+Bgbd61LUQCxXguvM6nGw+vbV7FP8Cl32J9S9X64SocO8 rpLBqiRJK0nzXGu+AOSazUOTUNTjaVZ3teI1E3X7BBao9p3zCT902nDfDy2T1MkM1tmg l80RJTZqe5FQUl6bmQAeu9IvbHjuA8C48JlbI9h+AH7B9Q5fzE63f4O64Wuj0Vzj/4PQ E1Q428QOOj9A8UJIvOU91Yp1mVU6flUGKGGSY2D3FPikfIY4ALkkcALiZTppwoRsrGD+ h12SMKBedN5HnkgQeK6mQouzDwzfbbyEphDRHPxM5yQ8S5lVKu5OMVQHS2uy+E2XAsXQ PHIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gNwHQp+abnGkbVRbVu1pbGFEEh9vqf8MUlQTWlzs6xU=; b=g8EsLtpzqMy5B4wO8+lUJ1rstXn3GTpftgMKfpFPHo0rOuFroa6koOQDgv9NNq9VHT Ojv1euIJC6Sf20+8g3zvJjej57PDkqOLg2XpWJOJ4qrhCmor88B2AEVVudDiQ7RFVakZ Gcm2O8hXUCSh3XXqDRgM+idHosMnlX1VedGGtiN73J013z+65FtCmyu5zyRK+28/JgVO G9B9w/c/HPtI7jxqbZiuNLRT8DWGxNcMwWwJuJO87pUCsslbd+JUWbc1tWT1nNx3I3xx Csk9WsOCcuMQWXkfMUEJEQOMg/v2Mwf8Q9zbSFPlifavNqOuCiIcvck8z7nrLk3uODaE mAsA== X-Gm-Message-State: AOAM531/ZYbTCsnD1b6qSXnC6aaBRBqz3h3n9VXKUW9Z2G+t8TK2hjZO 7QzBRqPZOYyf7hAR8ZHrZbbyaRXhS9qnbw== X-Received: by 2002:a17:90a:2f84:b0:1dd:940:50e7 with SMTP id t4-20020a17090a2f8400b001dd094050e7mr63398243pjd.210.1654557300429; Mon, 06 Jun 2022 16:15:00 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:dd1c:9738:3e40:ffe0]) by smtp.gmail.com with ESMTPSA id 2-20020a170902c24200b00162523fdb8fsm10954623plg.252.2022.06.06.16.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 16:15:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =gaosong@loongson.cn, yangxiaojuan@loongson.cn, Song Gao Subject: [PULL 09/43] target/loongarch: Add fixed point extra instruction translation Date: Mon, 6 Jun 2022 16:14:16 -0700 Message-Id: <20220606231450.448443-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220606231450.448443-1-richard.henderson@linaro.org> References: <20220606231450.448443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Song Gao This includes: - CRC[C].W.{B/H/W/D}.W - SYSCALL - BREAK - ASRT{LE/GT}.D - RDTIME{L/H}.W, RDTIME.D - CPUCFG Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220606124333.2060567-10-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/helper.h | 4 ++ target/loongarch/insns.decode | 19 ++++++ target/loongarch/op_helper.c | 26 +++++++ target/loongarch/translate.c | 1 + target/loongarch/insn_trans/trans_extra.c.inc | 68 +++++++++++++++++++ 5 files changed, 118 insertions(+) create mode 100644 target/loongarch/insn_trans/trans_extra.c.inc diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 100622bfc2..638c2efc51 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -11,3 +11,7 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(asrtgt_d, TCG_CALL_NO_WG, void, env, tl, tl) + +DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) +DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) +DEF_HELPER_FLAGS_2(cpucfg, TCG_CALL_NO_RWG_SE, tl, env, tl) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 8d247aa68c..98774dbddb 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -17,6 +17,7 @@ &i imm &r_i rd imm &rr rd rj +&rr_jk rj rk &rrr rd rj rk &rr_i rd rj imm &hint_r_i hint rj imm @@ -28,6 +29,7 @@ # @i15 .... ........ ..... imm:15 &i @rr .... ........ ..... ..... rj:5 rd:5 &rr +@rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk @rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr @r_i20 .... ... imm:s20 rd:5 &r_i @rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i @@ -237,3 +239,20 @@ ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr + +# +# Fixed point extra instruction +# +crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr +crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr +crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr +crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr +crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr +crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr +crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr +crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr +break 0000 00000010 10100 ............... @i15 +syscall 0000 00000010 10110 ............... @i15 +asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk +asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk +cpucfg 0000 00000000 00000 11011 ..... ..... @rr diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index bd2db783c9..18e565ce7f 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -13,6 +13,8 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "internals.h" +#include "qemu/crc32c.h" +#include /* Exceptions helpers */ void helper_raise_exception(CPULoongArchState *env, uint32_t exception) @@ -55,3 +57,27 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk) do_raise_exception(env, EXCCODE_ADEM, GETPC()); } } + +target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz) +{ + uint8_t buf[8]; + target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1); + + m &= mask; + stq_le_p(buf, m); + return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); +} + +target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz) +{ + uint8_t buf[8]; + target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1); + m &= mask; + stq_le_p(buf, m); + return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff); +} + +target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj) +{ + return rj > 21 ? 0 : env->cpucfg[rj]; +} diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 01791bf1a2..b946dc4d5f 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -155,6 +155,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext) #include "insn_trans/trans_bit.c.inc" #include "insn_trans/trans_memory.c.inc" #include "insn_trans/trans_atomic.c.inc" +#include "insn_trans/trans_extra.c.inc" static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc new file mode 100644 index 0000000000..549f75a867 --- /dev/null +++ b/target/loongarch/insn_trans/trans_extra.c.inc @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2021 Loongson Technology Corporation Limited + */ + +static bool trans_break(DisasContext *ctx, arg_break *a) +{ + generate_exception(ctx, EXCCODE_BRK); + return true; +} + +static bool trans_syscall(DisasContext *ctx, arg_syscall *a) +{ + generate_exception(ctx, EXCCODE_SYS); + return true; +} + +static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a) +{ + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); + + gen_helper_asrtle_d(cpu_env, src1, src2); + return true; +} + +static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a) +{ + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); + + gen_helper_asrtgt_d(cpu_env, src1, src2); + return true; +} + +static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a) +{ + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + + gen_helper_cpucfg(dest, cpu_env, src1); + gen_set_gpr(a->rd, dest, EXT_NONE); + + return true; +} + +static bool gen_crc(DisasContext *ctx, arg_rrr *a, + void (*func)(TCGv, TCGv, TCGv, TCGv), + TCGv tsz) +{ + TCGv dest = gpr_dst(ctx, a->rd, EXT_SIGN); + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); + + func(dest, src2, src1, tsz); + gen_set_gpr(a->rd, dest, EXT_SIGN); + + return true; +} + +TRANS(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1)) +TRANS(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2)) +TRANS(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4)) +TRANS(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) +TRANS(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1)) +TRANS(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2)) +TRANS(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4)) +TRANS(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))