diff mbox series

[2/3] target/riscv: Remove generate_exception_mtval

Message ID 20220604231004.49990-3-richard.henderson@linaro.org
State Accepted
Commit 5dacdbaeaf7874d361dc95d07e30c86b72c9693d
Headers show
Series target/riscv: Fix issue 1060 | expand

Commit Message

Richard Henderson June 4, 2022, 11:10 p.m. UTC
The function doesn't set mtval, it sets badaddr. Move the set
of badaddr directly into gen_exception_inst_addr_mis and use
generate_exception.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/translate.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

Comments

Alistair Francis June 13, 2022, 12:22 a.m. UTC | #1
On Sun, Jun 5, 2022 at 9:13 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The function doesn't set mtval, it sets badaddr. Move the set
> of badaddr directly into gen_exception_inst_addr_mis and use
> generate_exception.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c | 11 ++---------
>  1 file changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9196aa71db..6e4bbea1cd 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -228,14 +228,6 @@ static void generate_exception(DisasContext *ctx, int excp)
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
>
> -static void generate_exception_mtval(DisasContext *ctx, int excp)
> -{
> -    gen_set_pc_imm(ctx, ctx->base.pc_next);
> -    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
> -    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
> -    ctx->base.is_jmp = DISAS_NORETURN;
> -}
> -
>  static void gen_exception_illegal(DisasContext *ctx)
>  {
>      tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> @@ -245,7 +237,8 @@ static void gen_exception_illegal(DisasContext *ctx)
>
>  static void gen_exception_inst_addr_mis(DisasContext *ctx)
>  {
> -    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
> +    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
> +    generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
>  }
>
>  static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9196aa71db..6e4bbea1cd 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -228,14 +228,6 @@  static void generate_exception(DisasContext *ctx, int excp)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void generate_exception_mtval(DisasContext *ctx, int excp)
-{
-    gen_set_pc_imm(ctx, ctx->base.pc_next);
-    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
-    ctx->base.is_jmp = DISAS_NORETURN;
-}
-
 static void gen_exception_illegal(DisasContext *ctx)
 {
     tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
@@ -245,7 +237,8 @@  static void gen_exception_illegal(DisasContext *ctx)
 
 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 {
-    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
+    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
+    generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
 }
 
 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)