diff mbox series

[29/71] target/arm: Add the SME ZA storage to CPUARMState

Message ID 20220602214853.496211-30-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Scalable Matrix Extension | expand

Commit Message

Richard Henderson June 2, 2022, 9:48 p.m. UTC
Place this late in the resettable section of the structure,
to keep the most common element offsets from being > 64k.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h     |  8 ++++++++
 target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

Comments

Peter Maydell June 6, 2022, 4:13 p.m. UTC | #1
On Thu, 2 Jun 2022 at 23:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Place this late in the resettable section of the structure,
> to keep the most common element offsets from being > 64k.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h     |  8 ++++++++
>  target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 44 insertions(+)

> diff --git a/target/arm/machine.c b/target/arm/machine.c
> index 285e387d2c..d9dff6576d 100644
> --- a/target/arm/machine.c
> +++ b/target/arm/machine.c
> @@ -167,6 +167,39 @@ static const VMStateDescription vmstate_sve = {
>          VMSTATE_END_OF_LIST()
>      }
>  };
> +
> +static const VMStateDescription vmstate_za_row = {
> +    .name = "cpu/sme/za_row",

This isn't a subsection, so it doesn't need to have the hierarchical
name. What it actually is is just the VMStateDescription for
an ARMVectorReg, right? We could give it a name that facilitates
maybe reusing it later if we have other ARMVectorRegs we want to
migrate. (The SVE ones are an awkward special case because of the
overlap with the FP regs.)

> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
> +static bool za_needed(void *opaque)
> +{
> +    ARMCPU *cpu = opaque;
> +
> +    /*
> +     * When ZA storage is disabled, its contents are discarded.
> +     * It will be zeroed when ZA storage is re-enabled.
> +     */
> +    return FIELD_EX64(cpu->env.svcr, SVCR, ZA);
> +}
> +
> +static const VMStateDescription vmstate_za = {
> +    .name = "cpu/sme",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = za_needed,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0,
> +                             vmstate_za_row, ARMVectorReg),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
>  #endif /* AARCH64 */
>
>  static bool serror_needed(void *opaque)
> @@ -887,6 +920,9 @@ const VMStateDescription vmstate_arm_cpu = {
>  #endif
>          &vmstate_serror,
>          &vmstate_irq_line_state,
> +#ifdef TARGET_AARCH64
> +        &vmstate_za,
> +#endif
>          NULL

I don't think there's any requirement for subsections to
be added only at the end of the list, so we could put this
next to the SVE one to avoid the extra ifdef.

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9bd8058afe..1bc7de1da1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -694,6 +694,14 @@  typedef struct CPUArchState {
     } keys;
 
     uint64_t scxtnum_el[4];
+
+    /*
+     * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
+     * as we do with vfp.zregs[].  Because this is so large, keep this toward
+     * the end of the reset area, to keep the offsets into the rest of the
+     * structure smaller.
+     */
+    ARMVectorReg zarray[ARM_MAX_VQ * 16];
 #endif
 
 #if defined(CONFIG_USER_ONLY)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 285e387d2c..d9dff6576d 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -167,6 +167,39 @@  static const VMStateDescription vmstate_sve = {
         VMSTATE_END_OF_LIST()
     }
 };
+
+static const VMStateDescription vmstate_za_row = {
+    .name = "cpu/sme/za_row",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static bool za_needed(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+
+    /*
+     * When ZA storage is disabled, its contents are discarded.
+     * It will be zeroed when ZA storage is re-enabled.
+     */
+    return FIELD_EX64(cpu->env.svcr, SVCR, ZA);
+}
+
+static const VMStateDescription vmstate_za = {
+    .name = "cpu/sme",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = za_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0,
+                             vmstate_za_row, ARMVectorReg),
+        VMSTATE_END_OF_LIST()
+    }
+};
 #endif /* AARCH64 */
 
 static bool serror_needed(void *opaque)
@@ -887,6 +920,9 @@  const VMStateDescription vmstate_arm_cpu = {
 #endif
         &vmstate_serror,
         &vmstate_irq_line_state,
+#ifdef TARGET_AARCH64
+        &vmstate_za,
+#endif
         NULL
     }
 };