| Message ID | 20220602214853.496211-29-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Scalable Matrix Extension | expand |
On Thu, 2 Jun 2022 at 23:22, Richard Henderson <richard.henderson@linaro.org> wrote: > > These are required to determine if various insns > are allowed to issue. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 2 ++ > target/arm/translate.h | 4 ++++ > target/arm/helper.c | 4 ++++ > target/arm/translate-a64.c | 2 ++ > 4 files changed, 12 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 1ae1b7122b..9bd8058afe 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3284,6 +3284,8 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) > FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) > FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) > FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) > +FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) > +FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) > > /* > * Helpers for using the above. > diff --git a/target/arm/translate.h b/target/arm/translate.h > index a492e4217b..fbd6713572 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -101,6 +101,10 @@ typedef struct DisasContext { > bool align_mem; > /* True if PSTATE.IL is set */ > bool pstate_il; > + /* True if PSTATE.SM is set. */ > + bool pstate_sm; > + /* True if PSTATE.ZA is set. */ > + bool pstate_za; > /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ > bool mve_no_pred; > /* > diff --git a/target/arm/helper.c b/target/arm/helper.c > index f852fd7644..3edecb56b6 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -13857,6 +13857,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, > } > if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { > DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); > + if (FIELD_EX64(env->svcr, SVCR, SM)) { > + DP_TBFLAG_A64(flags, PSTATE_SM, 1); > + } > + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); Why did you write these two differently? Don't they do the same thing (set the tb flag to the value of the bit in env->svcr) ? Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 6/6/22 08:58, Peter Maydell wrote: >> + if (FIELD_EX64(env->svcr, SVCR, SM)) { >> + DP_TBFLAG_A64(flags, PSTATE_SM, 1); >> + } >> + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); > > Why did you write these two differently? Don't they do the same > thing (set the tb flag to the value of the bit in env->svcr) ? A later patch adds to the IF. r~ > > Otherwise > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > thanks > -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1ae1b7122b..9bd8058afe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3284,6 +3284,8 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) +FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) +FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index a492e4217b..fbd6713572 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -101,6 +101,10 @@ typedef struct DisasContext { bool align_mem; /* True if PSTATE.IL is set */ bool pstate_il; + /* True if PSTATE.SM is set. */ + bool pstate_sm; + /* True if PSTATE.ZA is set. */ + bool pstate_za; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index f852fd7644..3edecb56b6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13857,6 +13857,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + DP_TBFLAG_A64(flags, PSTATE_SM, 1); + } + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } sctlr = regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f51d80d816..fdc035ad9a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14635,6 +14635,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->ata = EX_TBFLAG_A64(tb_flags, ATA); dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); + dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM); + dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs;
These are required to determine if various insns are allowed to issue. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 ++++ target/arm/helper.c | 4 ++++ target/arm/translate-a64.c | 2 ++ 4 files changed, 12 insertions(+)