| Message ID | 20220602214853.496211-26-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Scalable Matrix Extension | expand |
On Thu, 2 Jun 2022 at 23:19, Richard Henderson <richard.henderson@linaro.org> wrote: > > This cpreg is used to access two new bits of PSTATE > that are not visible via any other mechanism. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 6 ++++++ > target/arm/helper.c | 13 +++++++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 31f812eda7..31b764556c 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -258,6 +258,7 @@ typedef struct CPUArchState { > * nRW (also known as M[4]) is kept, inverted, in env->aarch64 > * DAIF (exception masks) are kept in env->daif > * BTYPE is kept in env->btype > + * SM and ZA are kept in env->svcr > * all other bits are stored in their correct places in env->pstate > */ > uint32_t pstate; > @@ -292,6 +293,7 @@ typedef struct CPUArchState { > uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ > uint32_t btype; /* BTI branch type. spsr[11:10]. */ > uint64_t daif; /* exception masks, in the bits they are in PSTATE */ > + uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ > > uint64_t elr_el[4]; /* AArch64 exception link regs */ > uint64_t sp_el[4]; /* AArch64 banked stack pointers */ > @@ -1428,6 +1430,10 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) > #define PSTATE_MODE_EL1t 4 > #define PSTATE_MODE_EL0t 0 > > +/* PSTATE bits that are accessed via SVCR and not stored in SPRS_ELx. */ "SPSR" > +FIELD(SVCR, SM, 0, 1) > +FIELD(SVCR, ZA, 1, 1) > + > /* Write a new value to v7m.exception, thus transitioning into or out > * of Handler mode; this may result in a change of active stack pointer. > */ > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 98de2c797f..366420385a 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6353,11 +6353,24 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, > return CP_ACCESS_OK; > } > > +static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + value &= R_SVCR_SM_MASK | R_SVCR_ZA_MASK; > + /* TODO: Side effects. */ > + env->svcr = value; > +} > + > static const ARMCPRegInfo sme_reginfo[] = { > { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, > .access = PL0_RW, .accessfn = access_tpidr2, > .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, > + { .name = "SVCR", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, > + .access = PL0_RW, .type = ARM_CP_SME, > + .fieldoffset = offsetof(CPUARMState, svcr), > + .writefn = svcr_write, .raw_writefn = raw_write }, > }; > #endif /* TARGET_AARCH64 */ What about the "MSR SVCR*, #<imm>" forms ? I had a quick scan through the subject lines of the rest of the patchset and didn't see them. thanks -- PMM
On 6/6/22 06:40, Peter Maydell wrote: > What about the "MSR SVCR*, #<imm>" forms ? I had a quick scan > through the subject lines of the rest of the patchset and didn't > see them. They get alias names of SMSTART and SMSTOP. Patch 30. r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 31f812eda7..31b764556c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -258,6 +258,7 @@ typedef struct CPUArchState { * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif * BTYPE is kept in env->btype + * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; @@ -292,6 +293,7 @@ typedef struct CPUArchState { uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ + uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ @@ -1428,6 +1430,10 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 +/* PSTATE bits that are accessed via SVCR and not stored in SPRS_ELx. */ +FIELD(SVCR, SM, 0, 1) +FIELD(SVCR, ZA, 1, 1) + /* Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 98de2c797f..366420385a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6353,11 +6353,24 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= R_SVCR_SM_MASK | R_SVCR_ZA_MASK; + /* TODO: Side effects. */ + env->svcr = value; +} + static const ARMCPRegInfo sme_reginfo[] = { { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, .access = PL0_RW, .accessfn = access_tpidr2, .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, + { .name = "SVCR", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, + .access = PL0_RW, .type = ARM_CP_SME, + .fieldoffset = offsetof(CPUARMState, svcr), + .writefn = svcr_write, .raw_writefn = raw_write }, }; #endif /* TARGET_AARCH64 */
This cpreg is used to access two new bits of PSTATE that are not visible via any other mechanism. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 13 +++++++++++++ 2 files changed, 19 insertions(+)