From patchwork Thu Jun 2 21:48:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578142 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp956799max; Thu, 2 Jun 2022 15:17:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNn9OOFJNDEGPVu5OnzxyvXUJQ9wv52ItkRowaek4sYKEIkyi4EqJBi+oRnFTrpmdV5YvC X-Received: by 2002:a05:6214:29c5:b0:464:5850:d57f with SMTP id gh5-20020a05621429c500b004645850d57fmr5024573qvb.126.1654208244011; Thu, 02 Jun 2022 15:17:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654208244; cv=none; d=google.com; s=arc-20160816; b=Py9dbxzmLKyfhUUaeU0rZe0KtKS8hZtZdva5B5dpyqIebJXdW38Qp4MtWu+5gGplNC jz3hN3Vmw3rI2AsKYvUXjQaS0qxiAr5he79WlEIGaQTZGaF5LB8FnrSMNchiCJKNQiJ8 V5jTetmjII4YcAVGXbMFt19q4BF/Ka9Ql/kxnNSnq9ncqrEBluyZJ3XhRISVtUGY4ryA HhYHDxBpoTS2jcAF2DzEou0guFaqRe3UvJd+zbSeAwyQBWyDL56O549ZjVLF8zzmrU8G S6TtfetlKTPUS776jVAZiUrBtvixYO2dUT4Ebzy70oz57GpaHXgBxXAYSlRxL85p7bE8 GbHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZXeHgaKxYRbNnut8rVp8kMGvsswCzp2UB1e+rQJPl1o=; b=NVcUE1iQJqp/8tpcPs1gmFerD7MrZKENgdQkWzjWtsLOfWd2KIVHZgt9mjVLf4eudO vGRbTBfgsfNJWqA/Mfz9/JbFh2dM2A4N1mSCmUR6tBIeQZwd0tGjAu0KRlH5hH9TFiU1 eirDJ4iL9izIpP/FON8PD8pu+uCvLonvaZlTsy9WSHLgnPN7+OjCaIW3utRmsfkaF9Kg frn3JQ8BAEb+32n8OXKEv+Zsr9WOFvsaAmw+aRSp8CYXFnXxGXmEdsjoV3gmZgH2ypTI T7fjqYCREg/rRfqtFmiqL+OoUyzWEjLIPbllli5YR7nwqRPhlJzx+4gYp44FgPugQ7pJ AmFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MO/d19AC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jn7-20020ad45de7000000b004646babae8csi2332780qvb.129.2022.06.02.15.17.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Jun 2022 15:17:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MO/d19AC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt87-0004WM-J5 for patch@linaro.org; Thu, 02 Jun 2022 18:17:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgw-0004qC-NO for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:18 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:43556) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgu-0000AC-Qa for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:18 -0400 Received: by mail-pg1-x52f.google.com with SMTP id s68so5789327pgs.10 for ; Thu, 02 Jun 2022 14:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZXeHgaKxYRbNnut8rVp8kMGvsswCzp2UB1e+rQJPl1o=; b=MO/d19ACxCCoy6qsYYB+ai06R5Z1kKfPygOWzoX0b4fwX+iqTgUVSu9aCfolQkiDQ2 XWqxHKAYAum7J1SaQ/WjsgxLSUZfxYkhv+ONWGK+5FhdnTT4HRxxHkbr1Q7z6YREcOcd Tz1UQ5w/QWklzKDmbf+lJIimzLQTbvAj5KJW6gcqiWw9hKZx17QEWtTNaaHW5BkFpPP2 m53lbojSk/9TxRXIiQ5GaVDfOxUdGr1X10NA3y28ch8TlRnRuwkp9zxzZypV0UgjXfRu qt3HmWmi7or1h74gGABbkvSthE5B6bee84DnZCxCuhzxvGGIhQk9wSch+bSJu/iXEQte Nydg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZXeHgaKxYRbNnut8rVp8kMGvsswCzp2UB1e+rQJPl1o=; b=e3+q3Poxob2FrYmwbHSTq4EHfeFGKkQIoMOkH85/yEQcO9a6jRrArhXWYCe+h3SH9V 9nRzdyGzxy8wDsU2Wg5TZzkVWGI4Qca3CD6gZz4DaZ56slPkRc+spml3QJXVcGT6FMdk 7h/A5hiTbapL54r1yA4CPhuYj0Wsuk+HforOkD1El+SrxL1gB4+5M35solicDPJyHfMy U50ZAYOmcJpPvcZM5tS46sCPRRqwPLPydaQrOZg9Tv4mzRfqcMMp0YOTs1IQ6fPfXptO Ue6mSvKSx5VFLoTxfcG40Um0zBe+XQkh+PHstlRCTtcLaJAb1o+gPibw64ydrGyk+BSn ioIw== X-Gm-Message-State: AOAM531nQWr3FJMJhe81f0IYcdP4x1lf/96C4XsPutFnmErTK8Q/rQx4 muqRGfJj/QBwrgPQKn2kb9Vx1XIYTGy2vg== X-Received: by 2002:a05:6a00:170b:b0:51b:cf4b:9187 with SMTP id h11-20020a056a00170b00b0051bcf4b9187mr4038553pfc.15.1654206555248; Thu, 02 Jun 2022 14:49:15 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 24/71] target/arm: Add ARM_CP_SME Date: Thu, 2 Jun 2022 14:48:06 -0700 Message-Id: <20220602214853.496211-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will be used for controlling access to SME cpregs. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 5 +++++ target/arm/translate-a64.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index d9b678c2f1..d30758ee71 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -113,6 +113,11 @@ enum { ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, + /* + * Flag: Access check for this sysreg is constrained by the + * ARM pseudocode function CheckSMEAccess(). + */ + ARM_CP_SME = 1 << 19, }; /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8bbd1b7f07..f51d80d816 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1186,6 +1186,22 @@ bool sve_access_check(DisasContext *s) return fp_access_check(s); } +/* + * Check that SME access is enabled, raise an exception if not. + * Note that this function corresponds to CheckSMEAccess and is + * only used directly for cpregs. + */ +static bool sme_access_check(DisasContext *s) +{ + if (s->sme_excp_el) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_AccessTrap, false), + s->sme_excp_el); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the @@ -1958,6 +1974,8 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; + } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { + return; } if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {