From patchwork Thu Jun 2 01:33:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578080 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp106463max; Wed, 1 Jun 2022 18:40:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx32Ezd0wbRP+0nyjRsSsn7xC3vVtcMp16hsrr6YOwBHP5pZ9SnLec7AIEFt3X6XYcUP6od X-Received: by 2002:a37:9b55:0:b0:6a3:4ac4:1594 with SMTP id d82-20020a379b55000000b006a34ac41594mr1938145qke.164.1654134053492; Wed, 01 Jun 2022 18:40:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134053; cv=none; d=google.com; s=arc-20160816; b=DP3Oi2ihokWLzgyFOecqoOIa9nw5p8cxHbeWhJmV/LzQGWz03iV5zk4OmhyNgGFuBb jFn49RRRiYu46HBduTRCJNUhRz7wj2J7AL6l/h9OjrljSi8cXohkKLdD+rn0FOfj67dF WzwlaiWF9CfIRw4UOOg+WMRZej1QI7glTNuL+hu05Z7Zqy1eKCJzRic6ZrR/vkN9oivh ztEF0LkvcuNDpfmQ+fdiaD44o+WegLsUctWKLvC2Y9A7HgfJ+uyfOWpZprs33CW8x6x2 nVsRII3r1vrvcy3jpfHZXjjIcUlNV8fjFY+LYCbXN+LZ0QDE/xqA5vMV5T/7bKAbnaGv UC6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9h8O/PKdXL0KvuNK2v2gIq3YV3vKmkNQsNhTF8q3vR8=; b=lFiJkPGAOCq6yI2ibSxNGSJVd9E0+lAcI/DBAI2teeiC4Q15w4tp7LHZN8aRfOOKC/ +CZSfiUGkBK1m+GuilbIujo05tTXPrkoGmqpNH+RsC4RRS9qnsKvwL1NzaUh3suznoSj SpXly+JDWXZwStx5GrpvJKpe2ASzSH4RaT7rx/AsPDJNLhM5+IWbUjL2B7l6NiWAaZ8w EJfqobcNEt8U5EWmSKuoLxQJtRC04QtYYl0Sg7qbkZMiAybIbcmMlMOpA/VnlMG3Zie7 mcFeVcwwCOhnvqJgl7HbtssroL1HdPVtVvf8VjLxSaQ5RaNKseEQ4R8gSAAiDG16bHV3 rQqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M27HBWjA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s16-20020a05620a29d000b006a66d3bf118si1361504qkp.493.2022.06.01.18.40.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 01 Jun 2022 18:40:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M27HBWjA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwZpV-0008PB-0T for patch@linaro.org; Wed, 01 Jun 2022 21:40:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwZj6-0002Tg-FE for qemu-devel@nongnu.org; Wed, 01 Jun 2022 21:34:16 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:41732) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwZj4-0005FX-16 for qemu-devel@nongnu.org; Wed, 01 Jun 2022 21:34:16 -0400 Received: by mail-pj1-x102e.google.com with SMTP id l20-20020a17090a409400b001dd2a9d555bso3615631pjg.0 for ; Wed, 01 Jun 2022 18:34:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9h8O/PKdXL0KvuNK2v2gIq3YV3vKmkNQsNhTF8q3vR8=; b=M27HBWjAQRRPuK1DpaBilH8Fkn0tTTOKOu2MvD1zY8+Vl+gtKZPaU40ick/1WEVh3e 9OkjSUABFgC3qT2B+VWHGwQru1Eiu00xNsNUlKVIsGvQMwJJibtXW5ThQ+BEhUCIfg3e KA0TQOeE+GSk4Jmisi89BHwxNVraVmvRlHR8tvlfTH7sCySf+mPMSLH015nhKU8L7bKN eIMTd4bETfrqrxnDVYqSDgM5+ChJILqFcCvz9LET92HTxOoh2HiegZU0/cZYSZOvAhVM aIbWC0v6MIZPdGWhORbyLjkXE6jGpqvZJ8ZW/YryGhUv17vXB7/xihSyGl2xZIJqa+xe HNDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9h8O/PKdXL0KvuNK2v2gIq3YV3vKmkNQsNhTF8q3vR8=; b=E+H5WC70y4Vkq16UbePaIFrtEucqVlenAEsqM/dhFHGpgR1Iaad+jIQ5gTYTRYvyCB ttVHXeJBXFdTfvgNqmJB9JnLFovrpK3wgluUO1wyul5ZoFoMEbmeK90QnQDBK0RjbUWP akPpcfkMNxnoQGWd/fsUUdJpa5AsYFVPxpNyf7yrfqdQPPOgtSjeM4zSt3MhVo/2XP85 YrUOkex+t/lF/mpTho6UprOGxne8F2e8OXHob0daYIAWS0jGo7gXsqdoHtdj7fCwybKj hok2A0+lu2tdZqNV9+IkjrQvUMMhSHeVRjAfVDEB9jCycp0pYVtX+jeFL/zdt8qnRv46 ZR9w== X-Gm-Message-State: AOAM532MGEJRmUvLB3xURMgSq34sta4m3nmLYghSQTvPtBwsSIiWVvbQ QLYy0lduHKAE/WXl0Prkl43T7UIehnqToQ== X-Received: by 2002:a17:903:249:b0:163:6dc0:b8b3 with SMTP id j9-20020a170903024900b001636dc0b8b3mr2287235plh.24.1654133652133; Wed, 01 Jun 2022 18:34:12 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 07/17] target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0 Date: Wed, 1 Jun 2022 18:33:51 -0700 Message-Id: <20220602013401.303699-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented as always cleared. Update helper_div* to take the instruction length as an argument and use raise_exception_format2. Hoist the reset of the C flag above the division by zero check. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/helper.h | 12 +++++----- linux-user/m68k/cpu_loop.c | 2 +- target/m68k/op_helper.c | 48 +++++++++++++++++++++++--------------- target/m68k/translate.c | 33 +++++++++++++------------- 4 files changed, 52 insertions(+), 43 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 0a6b4146f6..f016c4c1c2 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -1,12 +1,12 @@ DEF_HELPER_1(bitrev, i32, i32) DEF_HELPER_1(ff1, i32, i32) DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_3(divuw, void, env, int, i32) -DEF_HELPER_3(divsw, void, env, int, s32) -DEF_HELPER_4(divul, void, env, int, int, i32) -DEF_HELPER_4(divsl, void, env, int, int, s32) -DEF_HELPER_4(divull, void, env, int, int, i32) -DEF_HELPER_4(divsll, void, env, int, int, s32) +DEF_HELPER_4(divuw, void, env, int, i32, int) +DEF_HELPER_4(divsw, void, env, int, s32, int) +DEF_HELPER_5(divul, void, env, int, int, i32, int) +DEF_HELPER_5(divsl, void, env, int, int, s32, int) +DEF_HELPER_5(divull, void, env, int, int, i32, int) +DEF_HELPER_5(divsll, void, env, int, int, s32, int) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(cf_movec_to, void, env, i32, i32) DEF_HELPER_3(m68k_movec_to, void, env, i32, i32) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index e24d17e180..6598bce3c4 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -50,7 +50,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: - force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); break; case EXCP_TRAP0: { diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 750d65576f..729ee0e934 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -396,7 +396,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_ILLEGAL: - case EXCP_DIV0: case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ @@ -404,6 +403,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_CHK: + case EXCP_DIV0: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; @@ -574,18 +574,19 @@ raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr) cpu_loop_exit(cs); } -void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) +void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den, int ilen) { uint32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffff) { env->cc_v = -1; /* @@ -601,18 +602,19 @@ void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) env->cc_v = 0; } -void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) +void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den, int ilen) { int32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int16_t)quot) { env->cc_v = -1; /* nothing else is modified */ @@ -629,18 +631,20 @@ void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) env->cc_v = 0; } -void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divul)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint32_t num = env->dregs[numr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -657,18 +661,20 @@ void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) } } -void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsl)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int32_t num = env->dregs[numr]; int32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -685,19 +691,21 @@ void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) } } -void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divull)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); uint64_t quot; uint32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffffffffULL) { env->cc_v = -1; /* @@ -720,19 +728,21 @@ void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) env->dregs[numr] = quot; } -void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsll)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); int64_t quot; int32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int32_t)quot) { env->cc_v = -1; /* diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6d6d026e3c..d775345bfa 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1601,6 +1601,7 @@ DISAS_INSN(divw) int sign; TCGv src; TCGv destr; + TCGv ilen; /* divX.w ,Dn 32/16 -> 16r:16q */ @@ -1609,20 +1610,20 @@ DISAS_INSN(divw) /* dest.l / src.w */ SRC_EA(env, src, OS_WORD, sign, NULL); - destr = tcg_const_i32(REG(insn, 9)); + destr = tcg_constant_i32(REG(insn, 9)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsw(cpu_env, destr, src); + gen_helper_divsw(cpu_env, destr, src, ilen); } else { - gen_helper_divuw(cpu_env, destr, src); + gen_helper_divuw(cpu_env, destr, src, ilen); } - tcg_temp_free(destr); set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(divl) { - TCGv num, reg, den; + TCGv num, reg, den, ilen; int sign; uint16_t ext; @@ -1639,15 +1640,14 @@ DISAS_INSN(divl) /* divX.l , Dr:Dq 64/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsll(cpu_env, num, reg, den); + gen_helper_divsll(cpu_env, num, reg, den, ilen); } else { - gen_helper_divull(cpu_env, num, reg, den); + gen_helper_divull(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); return; } @@ -1656,15 +1656,14 @@ DISAS_INSN(divl) /* divXl.l , Dr:Dq 32/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsl(cpu_env, num, reg, den); + gen_helper_divsl(cpu_env, num, reg, den, ilen); } else { - gen_helper_divul(cpu_env, num, reg, den); + gen_helper_divul(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); }