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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bi12-20020a05600c3d8c00b003974b95d897sm10232152wmb.37.2022.05.30.09.07.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 May 2022 09:07:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 052/117] target/arm: Use TRANS_FEAT for do_index Date: Mon, 30 May 2022 17:06:03 +0100 Message-Id: <20220530160708.726466-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220530160708.726466-1-peter.maydell@linaro.org> References: <20220530160708.726466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220527181907.189259-50-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 35 ++++++++--------------------------- 1 file changed, 8 insertions(+), 27 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 44c23429232..dac29749ce0 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1126,33 +1126,14 @@ static bool do_index(DisasContext *s, int esz, int rd, return true; } -static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) -{ - TCGv_i64 start = tcg_constant_i64(a->imm1); - TCGv_i64 incr = tcg_constant_i64(a->imm2); - return do_index(s, a->esz, a->rd, start, incr); -} - -static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a) -{ - TCGv_i64 start = tcg_constant_i64(a->imm); - TCGv_i64 incr = cpu_reg(s, a->rm); - return do_index(s, a->esz, a->rd, start, incr); -} - -static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a) -{ - TCGv_i64 start = cpu_reg(s, a->rn); - TCGv_i64 incr = tcg_constant_i64(a->imm); - return do_index(s, a->esz, a->rd, start, incr); -} - -static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a) -{ - TCGv_i64 start = cpu_reg(s, a->rn); - TCGv_i64 incr = cpu_reg(s, a->rm); - return do_index(s, a->esz, a->rd, start, incr); -} +TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd, + tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2)) +TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd, + tcg_constant_i64(a->imm), cpu_reg(s, a->rm)) +TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd, + cpu_reg(s, a->rn), tcg_constant_i64(a->imm)) +TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd, + cpu_reg(s, a->rn), cpu_reg(s, a->rm)) /* *** SVE Stack Allocation Group