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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 01/18] target/arm: Allow raise_exception to handle finding target EL Date: Mon, 23 May 2022 13:47:25 -0700 Message-Id: <20220523204742.740932-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The work of finding the correct target EL for an exception is currently split between raise_exception and target_exception_el. Begin merging these by allowing the input to raise_exception to be zero and use exception_target_el for that case. Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 ++++++----- target/arm/op_helper.c | 13 +++++++++---- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b654bee468..03363b0f32 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -111,18 +111,19 @@ FIELD(DBGWCR, SSCE, 29, 1) /** * raise_exception: Raise the specified exception. * Raise a guest exception with the specified value, syndrome register - * and target exception level. This should be called from helper functions, - * and never returns because we will longjump back up to the CPU main loop. + * and the current or target exception level. This should be called from + * helper functions, and never returns because we will longjump back up + * to the CPU main loop. */ G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el); + uint32_t syndrome, uint32_t cur_or_target_el); /* * Similarly, but also use unwinding to restore cpu state. */ G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el, - uintptr_t ra); + uint32_t syndrome, + uint32_t cur_or_target_el, uintptr_t ra); /* * For AArch64, map a given EL to an index in the banked_spsr array. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c4bd668870..6b9141b79a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,10 +28,15 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) -void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t cur_or_target_el) { CPUState *cs = env_cpu(env); + int target_el = cur_or_target_el; + + if (cur_or_target_el == 0) { + target_el = exception_target_el(env); + } if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* @@ -54,7 +59,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, } void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, - uint32_t target_el, uintptr_t ra) + uint32_t cur_or_target_el, uintptr_t ra) { CPUState *cs = env_cpu(env); @@ -64,7 +69,7 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, * the caller passed us, and cannot use cpu_loop_exit_restore(). */ cpu_restore_state(cs, ra, true); - raise_exception(env, excp, syndrome, target_el); + raise_exception(env, excp, syndrome, cur_or_target_el); } uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,