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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id j7-20020a056a00130700b004b9f7cd94a4sm16482827pfu.56.2022.04.26.11.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 11:19:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/68] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields Date: Tue, 26 Apr 2022 11:18:25 -0700 Message-Id: <20220426181907.103691-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220426181907.103691-1-richard.henderson@linaro.org> References: <20220426181907.103691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation of the fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-27-richard.henderson@linaro.org> --- target/nios2/cpu.h | 8 ++++---- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 17 +++++++++-------- target/nios2/translate.c | 2 +- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index f8cd5dc218..a6811ff7ea 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -110,10 +110,10 @@ FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) #define CR_PTEADDR 8 -#define CR_PTEADDR_PTBASE_SHIFT 22 -#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) -#define CR_PTEADDR_VPN_SHIFT 2 -#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) + +FIELD(CR_PTEADDR, VPN, 2, 20) +FIELD(CR_PTEADDR, PTBASE, 22, 10) + #define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index b30740824c..c2d0afe1b6 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -286,8 +286,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; } - env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; - env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; + env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, + address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; cs->exception_index = excp; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 95900724e8..75afc56daf 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -97,7 +97,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g = (v & CR_TLBACC_G) ? 1 : 0; int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; @@ -148,7 +148,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ if (v & CR_TLBMISC_RD) { int way = (v >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; @@ -160,8 +160,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; - env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; + env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], + CR_PTEADDR, VPN, + entry->tag >> TARGET_PAGE_BITS); } else { env->ctrl[CR_TLBMISC] = v; } @@ -171,12 +172,12 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) { - trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, - (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); + trace_nios2_mmu_write_pteaddr(FIELD_EX32(v, CR_PTEADDR, PTBASE), + FIELD_EX32(v, CR_PTEADDR, VPN)); /* Writes to PTEADDR don't change the read-back VPN value */ - env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) | - (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)); + env->ctrl[CR_PTEADDR] = ((v & ~R_CR_PTEADDR_VPN_MASK) | + (env->ctrl[CR_PTEADDR] & R_CR_PTEADDR_VPN_MASK)); env->mmu.pteaddr_wr = v; } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index fc49a7101f..baa22c5101 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -924,7 +924,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, env->mmu.tlbacc_wr); #endif