From patchwork Fri Apr 22 10:03:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 564817 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp364987map; Fri, 22 Apr 2022 04:09:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxvu5Foh2i05H4a0hpmqpsQkMtlbV9vXWtT9NH8Igc6od1nG3TO3rhdDxIK8O3qqJXK5M2l X-Received: by 2002:a37:34b:0:b0:69e:5a7e:745e with SMTP id 72-20020a37034b000000b0069e5a7e745emr2234935qkd.385.1650625745601; Fri, 22 Apr 2022 04:09:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650625745; cv=none; d=google.com; s=arc-20160816; b=TFrVMkYrarOHRP8Le1kO9T4fNlqgKz6NtNNDX65owax4Moe5j0rRVHmKqOgwAJ85K3 4fBKXysS4Pm5JFmfAWcXNlaFU5PfR2beOsAKh4K/JH7NxiwI5MNEIRLobfXTqIgau9q+ WzMEoaXVmq8yobU7YQRnrdjc/1wKGkkVoDWrmY3fZvSNPVrhmYrIDj1NAiXC8v7Uk0NL 4euJQA8HaLJAefOhHCNUtwY2D6KA/w26eAFNz6P4Mn64bo27tSpSg3K7mfxzOZVfSifm 7lbYpvrBAchuKzDzRLNLJtlyP5Ur9EscUMDfTqL2JGfgeaUreGIVmyluBMlutORG2Cbs I3lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EjeZtA3tZWg+aDhUloJoLuwvQBqCQPUULzcGK3wHquE=; b=ZJPoHwa/QR80FVg7urs5j8YtgN9MqIy5jA2bSrEKzG3i3eE8G+5yoaLFbOgTOHZD46 zjN4utdO/6BygUUxWau24t0Oc7tX9y+54cFM3ebQEEAymNzhcEK7Bu4KSFHAI5uMEXWZ OKRYjcyVTK0f+3E7oexFmlv99WFDEfMxw1ELe/bmKb2a9LRKHcRUMOUv7CetfgvaNSW6 kYmW5igWqt/cKjmHdo0XJCjWLHR1o7JjnaK9azCB8RjzUo4iI/sdq0A+VRBXKq1Qa21l bWKlnfUZ2ETnN6iWLvGKWHWqC2JFR6k50YvdaEgnV0TRQeaHXR9kS1WZ3O5rOCt/kK5v goOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CXs5SrNZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p83-20020a37a656000000b0069e13f46f99si2034046qke.427.2022.04.22.04.09.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Apr 2022 04:09:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CXs5SrNZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhr9t-0005oz-07 for patch@linaro.org; Fri, 22 Apr 2022 07:09:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhq9t-0004fO-Sk for qemu-devel@nongnu.org; Fri, 22 Apr 2022 06:05:02 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:37785) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhq9s-0002e9-7m for qemu-devel@nongnu.org; Fri, 22 Apr 2022 06:05:01 -0400 Received: by mail-wr1-x429.google.com with SMTP id t6so6882787wra.4 for ; Fri, 22 Apr 2022 03:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EjeZtA3tZWg+aDhUloJoLuwvQBqCQPUULzcGK3wHquE=; b=CXs5SrNZLUu29Ysw4+S58yi4ltUAKYGZIS/E5z6NwVuDOM3hdf7A9KQQocUA1KiYGp TYOKdPQBg0AzaOTlmEeeHxcmlwbP4pQFDG+fyqVmdVP/Agi8KzOFHIEs3R2woywcC7tc 7YSEynFjMXGemp/TGB2D8yQqyBM1275tr+LZlZax7ha0p5kyEsRF4T4VFJ/U4Jzz3pfS tcS1O12myO+9WD1h5gS+7eKcG9BneDLcoFp+dk1RUxcb2cldjE09Mg2sazB8kRooE6ya 8MjXzqqWe0Sg7lyw7G5ulgXdxn28Qc5dBxRHJzgLU6tDsBNCOGTUM7kmAT3Vdh1WcwuT k0/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EjeZtA3tZWg+aDhUloJoLuwvQBqCQPUULzcGK3wHquE=; b=RF8QjrqCP2+zhvOs4FVliRVT+9sIVylBrTLEaiDryzAkK1rvbPInHiPUWI0cYcw+Sm 5ylDfCiBVaNMAUymHZRfSie/lt53DI9KQFPYyEWYM4eLnbF/SkCNs+g+uZ+8m4OiDbaH 1smOWHM440gV83QVNIpiKo2Ukz+Jo4MXN+DXV3hH6NmU0EOLMxGHGEfTwQpTI+gZHHaL dyJpERli4QmQlzp7J/WJwNHf/4IsFLxitVF4KQv9RJ7ZIaHhmOoYvxcff8W3nmV89j4V 7kbvZ9tN/7pqVtHqbYHme4uGUtaBkak/e+1xiNmuz67HPpQRuY8Qsn1BN1TBNxtJE2MO efeA== X-Gm-Message-State: AOAM533lkKRB2tyg3nAzlUHGL7LEGvErXCe7Q3WvSPeNmWNYi6FiYL7K BicHGC/p03qPKdB0tlFj57qNR5hsxnllLg== X-Received: by 2002:adf:db8b:0:b0:207:9a90:3819 with SMTP id u11-20020adfdb8b000000b002079a903819mr3133255wri.617.1650621898411; Fri, 22 Apr 2022 03:04:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a05600c2dd000b0038ed449cbdbsm4312148wmh.3.2022.04.22.03.04.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 03:04:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/61] hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily Date: Fri, 22 Apr 2022 11:03:57 +0100 Message-Id: <20220422100432.2288247-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422100432.2288247-1-peter.maydell@linaro.org> References: <20220422100432.2288247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The maintenance interrupt state depends only on: * ICH_HCR_EL2 * ICH_LR_EL2 * ICH_VMCR_EL2 fields VENG0 and VENG1 Now we have a separate function that updates only the vIRQ and vFIQ lines, use that in places that only change state that affects vIRQ and vFIQ but not the maintenance interrupt. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220408141550.1271295-27-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index f11863ff613..d627ddac90f 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -543,7 +543,7 @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); return; } @@ -588,7 +588,7 @@ static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, write_vbpr(cs, grp, value); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -615,7 +615,7 @@ static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, ICH_VMCR_EL2_VPMR_LENGTH, value); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -682,7 +682,7 @@ static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT, 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2452,7 +2452,7 @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t ich_hcr_read(CPUARMState *env, const ARMCPRegInfo *ri)