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[PULL,7/7] target/rx: update PC correctly in wait instruction

Message ID 20220421173114.48357-8-richard.henderson@linaro.org
State Accepted
Commit 724eaecec6d22cf3842f896684bdc5b79492f093
Headers show
Series [PULL,1/7] target/rx: Put tb_flags into DisasContext | expand

Commit Message

Richard Henderson April 21, 2022, 5:31 p.m. UTC 
From: Tomoaki Kawada <i@yvt.jp>

`cpu_pc` at this point does not necessary point to the current
instruction (i.e., the wait instruction being translated), so it's
incorrect to calculate the new value of `cpu_pc` based on this. It must
be updated with `ctx->base.pc_next`, which contains the correct address
of the next instruction.

This change fixes the wait instruction skipping the subsequent branch
when used in an idle loop like this:

    0:  wait
        bra.b 0b
        brk   // should be unreachable

Signed-off-by: Tomoaki Kawada <i@yvt.jp>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220417060224.2131788-1-i@yvt.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/rx/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target/rx/translate.c b/target/rx/translate.c
index 63c062993e..62aee66937 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2285,7 +2285,7 @@  static bool trans_INT(DisasContext *ctx, arg_INT *a)
 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
 {
     if (is_privileged(ctx, 1)) {
-        tcg_gen_addi_i32(cpu_pc, cpu_pc, 2);
+        tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
         gen_helper_wait(cpu_env);
     }
     return true;