diff mbox series

[v1,10/15] cputlb: add tracepoints for TB invalidation

Message ID 20220408164742.2844631-11-alex.bennee@linaro.org
State New
Headers show
Series testing, docs, tracepoints and cputlb hacks | expand

Commit Message

Alex Bennée April 8, 2022, 4:47 p.m. UTC 
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 accel/tcg/translate-all.c | 2 ++
 accel/tcg/trace-events    | 1 +
 2 files changed, 3 insertions(+)

Comments

Richard Henderson April 9, 2022, 4:10 p.m. UTC | #1 
On 4/8/22 09:47, Alex Bennée wrote:
> Signed-off-by: Alex Bennée<alex.bennee@linaro.org>
> ---
>   accel/tcg/translate-all.c | 2 ++
>   accel/tcg/trace-events    | 1 +
>   2 files changed, 3 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index e9f1cc179d..b0009177b9 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1180,6 +1180,8 @@  static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
 
     assert_memory_lock();
 
+    trace_tb_phys_invalidate(tb, tb->pc);
+
     /* make sure no further incoming jumps will be chained to this TB */
     qemu_spin_lock(&tb->jmp_lock);
     qatomic_set(&tb->cflags, tb->cflags | CF_INVALID);
diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events
index e11e59492f..c034649dc2 100644
--- a/accel/tcg/trace-events
+++ b/accel/tcg/trace-events
@@ -14,5 +14,6 @@  memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size) "
 memory_notdirty_set_dirty(uint64_t vaddr) "0x%" PRIx64
 
 # translate-all.c
+tb_phys_invalidate(void *tb, uintptr_t pc) "tb:%p, pc:0x%"PRIxPTR""
 tb_invalidate_phys_page_fast(uint64_t page_start, int len, uint64_t ret, int wc, void *bmap) "addr:0x%" PRIx64 "/%d pc:0x%" PRIx64" wc:%d/%p"
 translate_block(void *tb, uintptr_t pc, const void *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p"