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[v5,03/48] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS

Message ID	20220310112725.570053-4-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v5 03/48] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Date: Thu, 10 Mar 2022 03:26:40 -0800 Message-Id: <20220310112725.570053-4-richard.henderson@linaro.org> In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/nios2: Shadow register set, EIC and VIC \| expand [v5,00/48] target/nios2: Shadow register set, EIC and VIC [v5,01/48] target/nios2: Check supervisor on eret [v5,02/48] target/nios2: Stop generating code if gen_check_supervisor fails [v5,03/48] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS [v5,04/48] target/nios2: Split PC out of env->regs[] [v5,05/48] target/nios2: Split out helper for eret instruction [v5,06/48] target/nios2: Fix BRET instruction [v5,07/48] target/nios2: Do not create TCGv for control registers [v5,08/48] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs [v5,09/48] target/nios2: Remove cpu_interrupts_enabled [v5,10/48] target/nios2: Split control registers away from general registers [v5,11/48] target/nios2: Do not zero the general registers on reset [v5,12/48] target/nios2: Clean up nios2_cpu_dump_state [v5,13/48] target/nios2: Use hw/registerfields.h for CR_STATUS fields [v5,14/48] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields [v5,15/48] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields [v5,16/48] target/nios2: Use hw/registerfields.h for CR_TLBACC fields [v5,17/48] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE [v5,18/48] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields [v5,19/48] target/nios2: Move R_FOO and CR_BAR into enumerations [v5,20/48] target/nios2: Create EXCP_SEMIHOST for semi-hosting [v5,21/48] target/nios2: Clean up nios2_cpu_do_interrupt [v5,22/48] target/nios2: Hoist CPU_LOG_INT logging [v5,23/48] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND [v5,24/48] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt [v5,25/48] target/nios2: Clean up handling of tlbmisc in do_exception [v5,26/48] target/nios2: Prevent writes to read-only or reserved control fields [v5,27/48] target/nios2: Implement cpuid [v5,28/48] target/nios2: Implement CR_STATUS.RSIE [v5,29/48] target/nios2: Remove CPU_INTERRUPT_NMI [v5,30/48] target/nios2: Support division error exception [v5,31/48] target/nios2: Use tcg_constant_tl [v5,32/48] target/nios2: Introduce dest_gpr [v5,33/48] target/nios2: Drop CR_STATUS_EH from tb->flags [v5,34/48] target/nios2: Enable unaligned traps for system mode [v5,35/48] target/nios2: Create gen_jumpr [v5,36/48] target/nios2: Hoist set of is_jmp into gen_goto_tb [v5,37/48] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY [v5,38/48] target/nios2: Use tcg_gen_lookup_and_goto_ptr [v5,39/48] target/nios2: Implement Misaligned destination exception [v5,40/48] linux-user/nios2: Handle various SIGILL exceptions [v5,41/48] target/nios2: Introduce shadow register sets [v5,42/48] target/nios2: Implement rdprs, wrprs [v5,43/48] target/nios2: Update helper_eret for shadow registers [v5,44/48] target/nios2: Implement EIC interrupt processing [v5,45/48] hw/intc: Vectored Interrupt Controller (VIC) [v5,46/48] hw/nios2: Introduce Nios2MachineState [v5,47/48] hw/nios2: Move memory regions into Nios2Machine [v5,48/48] hw/nios2: Machine with a Vectored Interrupt Controller

Commit Message

Richard Henderson March 10, 2022, 11:26 a.m. UTC

From: Amir Gonnen <amir.gonnen@neuroblade.ai>

Split NUM_CORE_REGS into components that can be used elsewhere.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai>
[rth: Split out of a larger patch for shadow register sets.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/nios2/cpu.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index ca0f3420cd..adeb16377d 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -56,9 +56,11 @@  struct Nios2CPUClass {
 #define EXCEPTION_ADDRESS     0x00000004
 #define FAST_TLB_MISS_ADDRESS 0x00000008
 
+#define NUM_GP_REGS 32
+#define NUM_CR_REGS 32
 
 /* GP regs + CR regs + PC */
-#define NUM_CORE_REGS (32 + 32 + 1)
+#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1)
 
 /* General purpose register aliases */
 #define R_ZERO   0
@@ -79,7 +81,7 @@  struct Nios2CPUClass {
 #define R_RA     31
 
 /* Control register aliases */
-#define CR_BASE  32
+#define CR_BASE  NUM_GP_REGS
 #define CR_STATUS    (CR_BASE + 0)
 #define   CR_STATUS_PIE  (1 << 0)
 #define   CR_STATUS_U    (1 << 1)