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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/33] target/nios2: Clean up nios2_cpu_do_interrupt Date: Mon, 7 Mar 2022 21:20:00 -1000 Message-Id: <20220308072005.307955-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Sink the bulk of the interrupt processing to the end of the file. All of the internal interrupt and non-interrupt exception code shares EH processing. Signed-off-by: Richard Henderson --- target/nios2/helper.c | 100 +++++++++++------------------------------- 1 file changed, 25 insertions(+), 75 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index a338d02f6b..ccf2634c9b 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -53,48 +53,25 @@ void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; + uint32_t exception_addr = cpu->exception_addr; + unsigned r_ea = R_EA; + unsigned cr_estatus = CR_ESTATUS; switch (cs->exception_index) { case EXCP_IRQ: - assert(env->status & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); - - env->estatus = env->status; - env->status |= CR_STATUS_IH; - env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); - - nios2_crs(env)[R_EA] = env->pc + 4; - env->pc = cpu->exception_addr; break; case EXCP_TLBD: - if ((env->status & CR_STATUS_EH) == 0) { + if (env->status & CR_STATUS_EH) { + qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); + /* Double TLB miss */ + env->tlbmisc |= CR_TLBMISC_DBL; + } else { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); - - /* Fast TLB miss */ - /* Variation from the spec. Table 3-35 of the cpu reference shows - * estatus not being changed for TLB miss but this appears to - * be incorrect. */ - env->estatus = env->status; - env->status |= CR_STATUS_EH; - env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->tlbmisc &= ~CR_TLBMISC_DBL; env->tlbmisc |= CR_TLBMISC_WR; - - nios2_crs(env)[R_EA] = env->pc + 4; - env->pc = cpu->fast_tlb_miss_addr; - } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); - - /* Double TLB miss */ - env->status |= CR_STATUS_EH; - env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->tlbmisc |= CR_TLBMISC_DBL; - - env->pc = cpu->exception_addr; + exception_addr = cpu->fast_tlb_miss_addr; } break; @@ -102,48 +79,18 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBW: case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); - - env->estatus = env->status; - env->status |= CR_STATUS_EH; - env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); - - if ((env->status & CR_STATUS_EH) == 0) { - env->tlbmisc |= CR_TLBMISC_WR; - } - - nios2_crs(env)[R_EA] = env->pc + 4; - env->pc = cpu->exception_addr; + env->tlbmisc |= CR_TLBMISC_WR; break; case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); - - if ((env->status & CR_STATUS_EH) == 0) { - env->estatus = env->status; - nios2_crs(env)[R_EA] = env->pc + 4; - } - - env->status |= CR_STATUS_EH; - env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc = cpu->exception_addr; break; case EXCP_ILLEGAL: case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); - - if ((env->status & CR_STATUS_EH) == 0) { - env->estatus = env->status; - nios2_crs(env)[R_EA] = env->pc + 4; - } - - env->status |= CR_STATUS_EH; - env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc = cpu->exception_addr; break; case EXCP_SEMIHOST: @@ -154,23 +101,26 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); - if ((env->status & CR_STATUS_EH) == 0) { - env->bstatus = env->status; - nios2_crs(env)[R_BA] = env->pc + 4; - } - - env->status |= CR_STATUS_EH; - env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc = cpu->exception_addr; + r_ea = R_BA; + cr_estatus = CR_BSTATUS; break; default: - cpu_abort(cs, "unhandled exception type=%d\n", - cs->exception_index); - break; + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); } + /* + * Finish Internal Interrupt or Noninterrupt Exception. + */ + + if (!(env->status & CR_STATUS_EH)) { + env->ctrl[cr_estatus] = env->status; + env->crs[r_ea] = env->pc + 4; + env->status |= CR_STATUS_EH; + } + env->status &= ~(CR_STATUS_PIE | CR_STATUS_U); + + env->pc = exception_addr; env->exception = FIELD_DP32(env->exception, CR_EXCEPTION, CAUSE, cs->exception_index); }