From patchwork Thu Mar 3 20:59:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547830 Delivered-To: patch@linaro.org Received: by 2002:ac0:f585:0:0:0:0:0 with SMTP id s5csp987002imq; Thu, 3 Mar 2022 13:15:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxYAyXNMZ7h2cXE+eSkHyfs870pUAnXUiBUub5Apr+PmsGPfwvuZJh7bv7irZ9QByhGUZ7F X-Received: by 2002:a25:8c10:0:b0:61d:b17e:703d with SMTP id k16-20020a258c10000000b0061db17e703dmr35427157ybl.154.1646342156283; Thu, 03 Mar 2022 13:15:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646342156; cv=none; d=google.com; s=arc-20160816; b=K2R16h8nigpJbM+ZScVvrLIwhdjJnTEhJFCS6wV9Nt7RI5gK+PvjXH83quspRg59Z1 AK/Y3wgibn1DstQk4ilsuuGNQS0jbJBljC1eB6v7AZ8nAcd1uQ+UIhijWfGScKtI3MR6 LU/H5aj+numvk7z0o5Px7DnhipJtTfOF0GezZcYwcIS/At2XPHN1wq5ZroT5MJ6hiO4g sUCv2VHtOeZKH+WS36kwyGgLMVKaHWCrE39AeHAU/tfcu2/JKujawgtr9RWePWdulvMj LxAokm4TN9+IG3nL5jw7R60szEQmYOX1n98dknGKRs7jZ50vAD2x66P4Up+0ZWA0q6hy zW9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EnmFxj+fZU2f2HHas6eAUj0uJ7KzSplIKT7ukEJg/z0=; b=vxs+ELpbyjm6qGxeFAKSYWdm88CIRx8LeQf9VqxZW7GkUmJ7CVZRLWlsHPtmC5Nukw TXuHwQ1nZCyL6OjWhEE/Viedxkw36179OdD8za3zYRPXf1SxzextJZwU70BjpsjGNKiV EobwZWrSCskUkfjL1y5UeXEBNcHla0oho+FlS0ljZj9T4co0Xi75iXvI02r1VXZoLvfs JnFCT9Sj4VC08+2hcpmN7MX0sE7zpX9gbSu1hVHGbkCeHVRqTdZOBtmP85CXm64SXCPD vnA4VxPF/d2AyOMFlBeEeJuIkfA02efwDEg5463wmU4smHpmDHTy+3toXHz83ARCKwi+ 3jIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hvctizwn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f8-20020a251f08000000b0061e0b190dc7si2585178ybf.658.2022.03.03.13.15.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Mar 2022 13:15:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hvctizwn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPsnj-0002pJ-NW for patch@linaro.org; Thu, 03 Mar 2022 16:15:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPsYU-00062T-Fx for qemu-devel@nongnu.org; Thu, 03 Mar 2022 16:00:10 -0500 Received: from [2607:f8b0:4864:20::1031] (port=55203 helo=mail-pj1-x1031.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPsYS-0004HZ-Hr for qemu-devel@nongnu.org; Thu, 03 Mar 2022 16:00:10 -0500 Received: by mail-pj1-x1031.google.com with SMTP id b8so5697167pjb.4 for ; Thu, 03 Mar 2022 13:00:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EnmFxj+fZU2f2HHas6eAUj0uJ7KzSplIKT7ukEJg/z0=; b=HvctizwnTdr3jcUbawyaHLhRcF5Zmc12wg4H3a7hgxwCa4G5GW3a7YZUyKhpjf3bl7 VFcICgwYq9Tg6Mh9/Q7I5VcBtQI4mEquwU/VZ4ZstF65vIgBpNxfQyccfXslSxsfyori WvMT56qfo0r9zcw7+n/JhnFIzkAy1xe8dgdS9p+DEejp8Cspxjyk+Xug/bZEnvKyuXsS OZJyN4xKKK2BG0tns08TKVEIPGSybE2/Yr2a+snQfGQV2cMTX2dwj0K2LTvgbnW/MDfd msfnNKd3Ao0uW/KMMT+ajwQ2gZYkSQRzicJ3RdP3O9Tnjpi3yjBqTaVWYpL0Zj9RLAUK THJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EnmFxj+fZU2f2HHas6eAUj0uJ7KzSplIKT7ukEJg/z0=; b=6s63mFOV0C0AreFgB5mTnf05GnWlrc+63RddKQCH2xMe0lm+N82MDeIZ2IoR9YKqOQ m3ryvXkk2rgukczjfZic0XPgBDnipm2W+XficwepLy9OcwnNPRW7LtQBXPCySUQnPONl 9VrgbTYuakkvdQ+pFz5pIcG+3zxmDFdpV6jv9GwLRDlUBRKnwBOnd5L0tqaItiJ9UgID +YL9LsgVIgu91H0Mop3luWsYws2dllXEfsMslxvjQxJBbTEBq040S6We/RwzVBDUWPOo mwqb0/e/+nv7r4rJC1Pjgn/W7yjZo2AmFns/wufJu7m1xtf24esJ1i53lGjZ/cIv3iEZ cM1g== X-Gm-Message-State: AOAM532sUjzVVkurz9UWz+EmkMHezPlltbrQIVYQK5FRv5/1/4yTu1il uJdCuZiyhbElSg+gXFbE37OxtBHcznhu2g== X-Received: by 2002:a17:90b:1e4b:b0:1bd:4c83:56a7 with SMTP id pi11-20020a17090b1e4b00b001bd4c8356a7mr7322732pjb.109.1646341207127; Thu, 03 Mar 2022 13:00:07 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. [2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id t8-20020a6549c8000000b00372eb3a7fb3sm2729934pgs.92.2022.03.03.13.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 13:00:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/30] tcg/i386: Implement avx512 variable rotate Date: Thu, 3 Mar 2022 10:59:27 -1000 Message-Id: <20220303205944.469445-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303205944.469445-1-richard.henderson@linaro.org> References: <20220303205944.469445-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" AVX512VL has VPROLVD and VPRORVQ. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 25 ++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 23a8b2a8c8..da1eff59aa 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -197,7 +197,7 @@ extern bool have_movbe; #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec have_avx512vl #define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_rotv_vec have_avx512vl #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 3a9f6a3360..712ae3a168 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -420,6 +420,10 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) #define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) +#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX) +#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) +#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX) +#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) #define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) @@ -2839,6 +2843,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, static int const umax_insn[4] = { OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 }; + static int const rotlv_insn[4] = { + OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ + }; + static int const rotrv_insn[4] = { + OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ + }; static int const shlv_insn[4] = { OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ }; @@ -2922,6 +2932,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_sarv_vec: insn = sarv_insn[vece]; goto gen_simd; + case INDEX_op_rotlv_vec: + insn = rotlv_insn[vece]; + goto gen_simd; + case INDEX_op_rotrv_vec: + insn = rotrv_insn[vece]; + goto gen_simd; case INDEX_op_shls_vec: insn = shls_insn[vece]; goto gen_simd; @@ -3275,6 +3291,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: @@ -3387,7 +3405,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) return 0; case INDEX_op_rotlv_vec: case INDEX_op_rotrv_vec: - return have_avx2 && vece >= MO_32 ? -1 : 0; + switch (vece) { + case MO_32: + case MO_64: + return have_avx512vl ? 1 : have_avx2 ? -1 : 0; + } + return 0; case INDEX_op_mul_vec: if (vece == MO_8) {