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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 7/7] target/nios2: Rewrite interrupt handling Date: Thu, 3 Mar 2022 10:46:24 -1000 Message-Id: <20220303204624.468786-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Previously, we would avoid setting CPU_INTERRUPT_HARD when interrupts are disabled at a particular point in time, instead queuing the value into cpu->irq_pending. This is more complicated than required. Instead, set CPU_INTERRUPT_HARD any time there is a pending interrupt, and exclusively check for interrupts disabled in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 1 - target/nios2/helper.h | 1 - target/nios2/cpu.c | 10 ++++------ target/nios2/op_helper.c | 19 ------------------- target/nios2/translate.c | 14 +++++--------- 5 files changed, 9 insertions(+), 36 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d2ba0c5bbd..a00e4229ce 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -160,7 +160,6 @@ struct CPUNios2State { #if !defined(CONFIG_USER_ONLY) Nios2MMU mmu; - uint32_t irq_pending; #endif int error_code; }; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 21ef7f0791..a44ecfdf7a 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -24,5 +24,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) -DEF_HELPER_1(check_interrupts, void, env) #endif diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 4cade61e93..6975ae4bdb 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -73,12 +73,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level) env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level); - env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE]; - - if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending = 0; + if (env->regs[CR_IPENDING]) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else if (!env->irq_pending) { + } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } } @@ -134,7 +131,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) CPUNios2State *env = &cpu->env; if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + (env->regs[CR_STATUS] & CR_STATUS_PIE) && + (env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) { cs->exception_index = EXCP_IRQ; nios2_cpu_do_interrupt(cs); return true; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index d729379e4d..caa885f7b4 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -21,28 +21,9 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/main-loop.h" -#if !defined(CONFIG_USER_ONLY) -static void nios2_check_interrupts(CPUNios2State *env) -{ - if (env->irq_pending && - (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending = 0; - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); - } -} - -void helper_check_interrupts(CPUNios2State *env) -{ - qemu_mutex_lock_iothread(); - nios2_check_interrupts(env); - qemu_mutex_unlock_iothread(); -} -#endif /* !CONFIG_USER_ONLY */ - void helper_raise_exception(CPUNios2State *env, uint32_t index) { CPUState *cs = env_cpu(env); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a5f8d20729..f89271dbed 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -491,19 +491,15 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) case CR_IPENDING: /* ipending is read only, writes ignored. */ break; + case CR_STATUS: + case CR_IENABLE: + /* If interrupts were enabled using WRCTL, trigger them. */ + dc->base.is_jmp = DISAS_UPDATE; + /* fall through */ default: tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); break; } - - /* If interrupts were enabled using WRCTL, trigger them. */ - if ((instr.imm5 + CR_BASE) == CR_STATUS) { - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_check_interrupts(cpu_env); - dc->base.is_jmp = DISAS_UPDATE; - } #endif }