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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id d16-20020a17090ad99000b001bcbc4247a0sm2901211pjv.57.2022.03.03.12.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:46:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 1/7] target/nios2: Remove mmu_read_debug Date: Thu, 3 Mar 2022 10:46:18 -1000 Message-Id: <20220303204624.468786-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303204624.468786-1-richard.henderson@linaro.org> References: <20220303204624.468786-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::533 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This functionality can be had via plugins, if desired. In the meantime, it is unused code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/helper.h | 1 - target/nios2/mmu.h | 1 - target/nios2/mmu.c | 20 -------------------- target/nios2/op_helper.c | 5 ----- target/nios2/translate.c | 17 ----------------- 5 files changed, 44 deletions(-) diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 6c8f0b5b35..6d8eec1814 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -21,7 +21,6 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_2(mmu_read_debug, void, env, i32) DEF_HELPER_3(mmu_write, void, env, i32, i32) DEF_HELPER_1(check_interrupts, void, env) #endif diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h index 4f46fbb82e..b7785b46c0 100644 --- a/target/nios2/mmu.h +++ b/target/nios2/mmu.h @@ -44,7 +44,6 @@ void mmu_flip_um(CPUNios2State *env, unsigned int um); unsigned int mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, target_ulong vaddr, int rw, int mmu_idx); -void mmu_read_debug(CPUNios2State *env, uint32_t rn); void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v); void mmu_init(CPUNios2State *env); diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 2545c06761..5616c39d54 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -35,26 +35,6 @@ #define MMU_LOG(x) #endif -void mmu_read_debug(CPUNios2State *env, uint32_t rn) -{ - switch (rn) { - case CR_TLBACC: - MMU_LOG(qemu_log("TLBACC READ %08X\n", env->regs[rn])); - break; - - case CR_TLBMISC: - MMU_LOG(qemu_log("TLBMISC READ %08X\n", env->regs[rn])); - break; - - case CR_PTEADDR: - MMU_LOG(qemu_log("PTEADDR READ %08X\n", env->regs[rn])); - break; - - default: - break; - } -} - /* rw - 0 = read, 1 = write, 2 = fetch. */ unsigned int mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a59003855a..61fc4dc903 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -26,11 +26,6 @@ #include "qemu/main-loop.h" #if !defined(CONFIG_USER_ONLY) -void helper_mmu_read_debug(CPUNios2State *env, uint32_t rn) -{ - mmu_read_debug(env, rn); -} - void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) { mmu_write(env, rn, v); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f9abc2fdd2..194c8ebafd 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -448,23 +448,6 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) gen_check_supervisor(dc); switch (instr.imm5 + CR_BASE) { - case CR_PTEADDR: - case CR_TLBACC: - case CR_TLBMISC: - { -#if !defined(CONFIG_USER_ONLY) - if (likely(instr.c != R_ZERO)) { - tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); -#ifdef DEBUG_MMU - TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE); - gen_helper_mmu_read_debug(cpu_R[instr.c], cpu_env, tmp); - tcg_temp_free_i32(tmp); -#endif - } -#endif - break; - } - default: if (likely(instr.c != R_ZERO)) { tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]);