From patchwork Wed Feb 23 22:31:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 545226 X-Google-Smtp-Source: ABdhPJxcXEHeN8VK4UpHfVUOtMxswYeb64o1neSQv3d15Zcqb+faKZ623LWzG1VynRtrl8EMoSyu X-Received: by 2002:a37:ad5:0:b0:4b2:a0b9:8307 with SMTP id 204-20020a370ad5000000b004b2a0b98307mr1387759qkk.544.1645656351517; Wed, 23 Feb 2022 14:45:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645656351; cv=none; d=google.com; s=arc-20160816; b=mvaukZnI+qapkFV5OkjqNn0u3ZtJ9dnDhBd9VB8/XatAilsKyd7fa1GEerLWf/0VgD Vsiuokv2anCsPdLlLHwThgxcaHio8UVpwJ4KDzdeRTu0U+Ii6qxI82Q6qZv1TwBlT3yg 9XEzMfB1wcIe0qHSeqjH7XhB1iaLS71bay+LzNMm/Gj+KQt8hvas7IWGsGiNHSnbkXqy YTOZixejuAyXSC5DtyAeFenSeU0AThipE8GRGlZtMxMsHzzI9meHKclRHWSo6SR+45lp Ewz+SXQS0XTybKX8QyQ3g0GoOW2MQBqydcSf6wz6mXSyijQwN4nWCanPAoSJpP+uQe4r hANw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TmxawEn4TT//u8dncYbu6ycL9fZfNNpmMP+qU1HcQZ0=; b=lWEsM4eXZULiGJIMp8Wj9r+VjLVUX07L2KaaRuI82XEqR35Y3U2/rI0EvVEl+0kBdD 6pUP/7rz/6oNPxFQ+FPadvvKaIzg+u5PfpNpr8Wt4ylqCj4RL2nZ5z/KYtvSE0i1kmwx Et3afMAVEAkZVLHoR8xjr+BI7yfx89WjnEwGjOjxMdUJS6Qies/ImZs6qxS3T08zoLtE ojxxONkZG5Je82glcudkszECYP6LBPFLWzEoJJ6qb4TyvEuNdCQ5cc6noLUqA9vRtECy 3TCK7nLv7GF0Ia5TqosZ7ooBHRiB/b0Dpw+KbXlJ7rcAZkjmk0PsszK+/iE5YHR5nAZL m53A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WMB2Erux; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g10si448668qvd.467.2022.02.23.14.45.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 Feb 2022 14:45:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WMB2Erux; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nN0OM-0004Wz-E4 for patch@linaro.org; Wed, 23 Feb 2022 17:45:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nN0Av-0006xC-CX for qemu-devel@nongnu.org; Wed, 23 Feb 2022 17:31:57 -0500 Received: from [2607:f8b0:4864:20::631] (port=42754 helo=mail-pl1-x631.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nN0At-0001Ej-8z for qemu-devel@nongnu.org; Wed, 23 Feb 2022 17:31:57 -0500 Received: by mail-pl1-x631.google.com with SMTP id p17so62072plo.9 for ; Wed, 23 Feb 2022 14:31:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TmxawEn4TT//u8dncYbu6ycL9fZfNNpmMP+qU1HcQZ0=; b=WMB2EruxU8tOMv86xci1GCeZnQzzwlFrwKXA+WdpfLvaDMd4xi/hu+S3AJHqEVLv1M +1UJLNqZFjVUepZCpdlhMwT90DX7tPPYe65gi3PjkJbfQNpvq+oNB9utjhfCC/3W7aPu Op7qkuVLuKUejRkOh+zXzw1WaeTNaTD1MImlfuGaWb5HNjKHt5PwGaoFE6YzE8X14cQ1 MP9lGdodL2GHUzi6ndbYxwCLOGcwBKXjc58ZtnyG2pAHW12HKc79UQ9MNk7zfXChoO5W 9HKe+obfwnr6YGnN/WzxJHMUNJu9Qe/TQLpUBNz9RDIMV1qoKX+l64PGyvlEYlsElYo5 fLsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TmxawEn4TT//u8dncYbu6ycL9fZfNNpmMP+qU1HcQZ0=; b=lsFtU74vyVVoJR4feAlaDCrlxS+WYYC8KJBH7YAxBiOMojuEG+o7iHsWbBqMwckpcW 1+W3HPvZJrfhPDaK5mDB/z7H6OHUYj/rytrUHONXvsiWx7/7S/+/z8aq64KztogN0lzm sYT5Us3pibvtT/AnIvUUlddUSy4xqUWnaEVQU3SmA7z+j5uhdUi/BnFVKwSrvAgg4lqQ It2rmrIe/IV44e6MYCYQXHcUGpYOLYGfN21aZq+mFuChxhsD7K1rMd6l/KvCoSTL1Qu4 /kMIL9TR4NJKYNMciYsVFKvwhelofUZUolWPnsI/loqQ+RnzniXQep2M1tm/dg7m0CFQ 7SyQ== X-Gm-Message-State: AOAM530CjSxOPxifevbvStA3+LQ3lNvMBJ/Ql9ZMa5SbosR60FmZSutL Y612KkJrWSRHSb7kTQi0/hPKlprBF9VuTg== X-Received: by 2002:a17:90a:4149:b0:1bc:ba63:247e with SMTP id m9-20020a17090a414900b001bcba63247emr964850pjg.173.1645655513960; Wed, 23 Feb 2022 14:31:53 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id f8sm533815pfv.100.2022.02.23.14.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 14:31:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/17] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA Date: Wed, 23 Feb 2022 12:31:28 -1000 Message-Id: <20220223223137.114264-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223223137.114264-1-richard.henderson@linaro.org> References: <20220223223137.114264-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::631 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The original A.a revision of the AArch64 ARM required that we force-extend the addresses in these registers from 49 bits. This language has been loosened via a combination of IMPLEMENTATION DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of the entire aligned address. This means that we do not have to consider whether or not FEAT_LVA is enabled, and decide from which bit an address might need to be extended. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c002100979..2eff30d18c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6423,11 +6423,18 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = env_archcpu(env); int i = ri->crm; - /* Bits [63:49] are hardwired to the value of bit [48]; that is, the - * register reads and behaves as if values written are sign extended. + /* * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) + * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if + * they contain the value written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * + * Therefore we are allowed to compare the entire register, which lets + * us avoid considering whether or not FEAT_LVA is actually enabled. */ - value = sextract64(value, 0, 49) & ~3ULL; + value &= ~3ULL; raw_write(env, ri, value); hw_watchpoint_update(cpu, i); @@ -6473,10 +6480,19 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) case 0: /* unlinked address match */ case 1: /* linked address match */ { - /* Bits [63:49] are hardwired to the value of bit [48]; that is, - * we behave as if the register was sign extended. Bits [1:0] are - * RES0. The BAS field is used to allow setting breakpoints on 16 - * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether bits [63:49] + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit + * of the VA field ([48] or [52] for FEAT_LVA), or whether the + * value is read as written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * Therefore we are allowed to compare the entire register, which + * lets us avoid considering whether FEAT_LVA is actually enabled. + * + * The BAS field is used to allow setting breakpoints on 16-bit + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether * a bp will fire if the addresses covered by the bp and the addresses * covered by the insn overlap but the insn doesn't start at the * start of the bp address range. We choose to require the insn and @@ -6489,7 +6505,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). */ int bas = extract64(bcr, 5, 4); - addr = sextract64(bvr, 0, 49) & ~3ULL; + addr = bvr & ~3ULL; if (bas == 0) { return; }