[PULL,15/32] MAINTAINERS: Remove myself (for raspi).

From: Andrew Baumann <Andrew.Baumann@microsoft.com>

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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/32] MAINTAINERS: Remove myself (for raspi).
Date: Fri, 28 Jan 2022 15:29:52 +0000
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Message ID	20220128153009.2467560-16-peter.maydell@linaro.org
State	Accepted
Commit	5212297c474c816f65b1ad6d0d0efe88a08ba6b9
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 15/32] MAINTAINERS: Remove myself (for raspi). Date: Fri, 28 Jan 2022 15:29:52 +0000 Message-Id: <20220128153009.2467560-16-peter.maydell@linaro.org> In-Reply-To: <20220128153009.2467560-1-peter.maydell@linaro.org> References: <20220128153009.2467560-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	[PULL,01/32] Update copyright dates to 2022 \| expand [PULL,01/32] Update copyright dates to 2022 [PULL,02/32] hw/armv7m: Fix broken VMStateDescription [PULL,03/32] hw/char/exynos4210_uart: Fix crash on trying to load VM state [PULL,04/32] rtc: Move RTC function prototypes to their own header [PULL,05/32] hw/misc: Add a model of Versal's PMC SLCR [PULL,06/32] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models [PULL,07/32] hw/arm/xlnx-versal: Connect Versal's PMC SLCR [PULL,08/32] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header [PULL,09/32] hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method [PULL,10/32] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller [PULL,11/32] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model [PULL,12/32] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g [PULL,13/32] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI [PULL,14/32] MAINTAINERS: Add an entry for Xilinx Versal OSPI [PULL,15/32] MAINTAINERS: Remove myself (for raspi). [PULL,16/32] scripts: Explain the difference between linux-headers and standard-headers [PULL,17/32] target/arm: Log CPU index in 'Taking exception' log [PULL,18/32] hw/intc/arm_gicv3_its: Add tracepoints [PULL,19/32] hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS [PULL,20/32] hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set [PULL,21/32] hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER [PULL,22/32] hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs [PULL,23/32] hw/intc/arm_gicv3_its: Sort ITS command list into numeric order [PULL,24/32] hw/intc/arm_gicv3_redist: Remove unnecessary zero checks [PULL,25/32] hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported [PULL,26/32] hw/intc/arm_gicv3_its: Provide read accessor for translation_ops [PULL,27/32] hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers [PULL,28/32] hw/intc/arm_gicv3_its: Check table bounds against correct limit [PULL,29/32] hw/intc/arm_gicv3_its: Implement MOVALL [PULL,30/32] hw/intc/arm_gicv3_its: Implement MOVI [PULL,31/32] hw/arm: ast2600: Fix address mapping of second SPI controller [PULL,32/32] target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp

[PULL,15/32] MAINTAINERS: Remove myself (for raspi).

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