From patchwork Thu Jan 20 12:36:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 533588 Delivered-To: patch@linaro.org Received: by 2002:ac0:f7d2:0:0:0:0:0 with SMTP id i18csp58990imr; Thu, 20 Jan 2022 10:38:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJzbyDV1HILH3ToGcr+1Z+zoY5584MqWAma3RkAahDcmQhxGY7Zp6QUHgy6gLGuALB1rUTn5 X-Received: by 2002:a05:6902:1141:: with SMTP id p1mr492721ybu.261.1642703912592; Thu, 20 Jan 2022 10:38:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1642703912; cv=none; d=google.com; s=arc-20160816; b=XRhQYlI37x2OOS2B5ejii3tFV7BoVL0WKibv44qOrDlZPK+nEAf1WjYtY23c+IPyNT BBVGBvzGZSAP3FqtTin8YdHH9Xn0DBwhII/jO/TiH2FsRBFQViTgesy454u3vKiJoFIy xXAdvMxS+ZV4NixaQSvmpnItd74ptPKeTBK3fQKbta+LpyUWTGCic3o7xNh3sN/DsJTW WmrpxP6RbYe6IeGHgz5Vnam9M2vEx7ZjJpZ1Vy/+hr0/sxPwlIQlIPeG8hhD1rQQK7yQ Kc/CsnGauSIIUIohT0/wdEYSqsAGYri81zwZ5NZ56p0BREta4B8JknxUKnumlUvB0OpW D6Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FV6II8ZvS26ggR3zDxlxn/8r1SJGmBVBBb/p5eFPFnU=; b=LBFr67vjhG02Fh+WfhJp+Wpq7r4guwAHRL8GuO+Jjsy8tHVamRdRZ3H60H4auQaoZ5 FTQljyGm+Rs5NR9uCzlaMpSuzYNg+DFmh6tThElU7ujUpv8VaOwdYkOGyCM3WW9bjl2Z IUBwDucE1buFmoKs7iV3+u8ybHnQniMP/Z5NZpnBM2KEavr085thuyAjNpLCslf6e+T9 e/DHQXoDYCqxmPFebO0MphOWsIZBsRfgkkA18DLqbPKbpNM0VanPhuBsYCQjfktoCY2h HnRa73gIuUpsTM4iJqU6To/tOQ0dnfq+8G6zFCDBweB5PLOeGEiyrSUZx4C43cBwRqlp 62cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kuHE566h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q127si186944ywb.291.2022.01.20.10.38.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 20 Jan 2022 10:38:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kuHE566h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAcKH-0004eW-Ug for patch@linaro.org; Thu, 20 Jan 2022 13:38:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWgm-0004Jk-0C for qemu-devel@nongnu.org; Thu, 20 Jan 2022 07:37:16 -0500 Received: from [2a00:1450:4864:20::32c] (port=40954 helo=mail-wm1-x32c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nAWgh-0003JM-Q0 for qemu-devel@nongnu.org; Thu, 20 Jan 2022 07:37:13 -0500 Received: by mail-wm1-x32c.google.com with SMTP id r9-20020a1c4409000000b0034e043aaac7so478103wma.5 for ; Thu, 20 Jan 2022 04:37:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FV6II8ZvS26ggR3zDxlxn/8r1SJGmBVBBb/p5eFPFnU=; b=kuHE566h+TwPCGujnAHerLS3A0i3cRCSBjPX3pI8VYmWviV/HyEgYDAKhv3nBzTQjV mYKww9c0XC0B+05KINmWPQOej9KoMf19gbgb8vthfUrtpYRdeQ3xsxow12KRhZAg6sGe 0aJYl6OTNmiKjv1MMGobiE8G5f6UhCpfEjxWeRAIVx2yMrGizSawSxFBkJcF187oZ1Fp FJMEpinF43yRWu/r+Q+PV0bjJx7iocyKRahu9iw/VKu9dHjG7u1YfVgRVqbtFmA1jma8 Ih8eF0lhYbhZ5EZ79jSjCs2Se/fbsfN+Q110tF2hlZRhYiWSTzT3xkGcxF/yzhCdwEc1 GoyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FV6II8ZvS26ggR3zDxlxn/8r1SJGmBVBBb/p5eFPFnU=; b=GJhG2G4jGgWSaNl9ZMu7c4+kgAuJRl8dagXAr1LZmPniAqeTqtFsCHj+BY7EfROHNo Vs6zNlE/mUYYL0nxdV4pVi3rFSfO6pmd5eRnbO8oLv/+nJHG/S+BARtj+mXky4D7kv9l hJc184i6ZvJjdAm1dfBii+GFDgVagGHhKqUeA5etWf66fpy6T4RyMQd3E422haFoCd0m usETGlSPftVhOUjNy182xYoPe9loZ9AWt8cOQeSYq1KNYwPEn8Lq4DXXekpPtwmScqjb KTDgllIs51VLRNkjZfujb6i1zFPwclY3XIwt0jEJ/xC3+J/Ebpc2UNX1lMvvhUBaaJKc uLRg== X-Gm-Message-State: AOAM532FXaUYxYBhBuevaQrB7cPlYYO1i0Ak1GZJyviuyXx3bEyW2rKQ UPjFYQ0CmRpV6KPm5cFDA3vzBL+s5Ggp2A== X-Received: by 2002:adf:fa91:: with SMTP id h17mr418725wrr.189.1642682225095; Thu, 20 Jan 2022 04:37:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t8sm7993324wmq.43.2022.01.20.04.37.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 04:37:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/38] hw/intc/arm_gicv3_its: Use enum for return value of process_* functions Date: Thu, 20 Jan 2022 12:36:21 +0000 Message-Id: <20220120123630.267975-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120123630.267975-1-peter.maydell@linaro.org> References: <20220120123630.267975-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When an ITS detects an error in a command, it has an implementation-defined (CONSTRAINED UNPREDICTABLE) choice of whether to ignore the command, proceeding to the next one in the queue, or to stall the ITS command queue, processing nothing further. The behaviour required when the read of the command packet from memory fails is less clearly documented, but the same set of choices as for command errors seem reasonable. The intention of the QEMU implementation, as documented in the comments, is that if we encounter a memory error reading the command packet or one of the various data tables then we should stall, but for command parameter errors we should ignore the queue and continue. However, we don't actually do this. To get the desired behaviour, the various process_* functions need to return true to cause process_cmdq() to advance to the next command and keep processing, and false to stall command processing. What they mostly do is return false for any kind of error. To make the code clearer, replace the 'bool' return from the process_ functions with an enum which may be either CMD_STALL or CMD_CONTINUE. In this commit no behaviour changes; in subsequent commits we will adjust the error-return paths for the process_ functions one by one. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220111171048.3545974-6-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its.c | 59 ++++++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 21 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index c1f76682d04..10901a5e709 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -45,6 +45,23 @@ typedef struct { uint64_t itel; } IteEntry; +/* + * The ITS spec permits a range of CONSTRAINED UNPREDICTABLE options + * if a command parameter is not correct. These include both "stall + * processing of the command queue" and "ignore this command, and + * keep processing the queue". In our implementation we choose that + * memory transaction errors reading the command packet provoke a + * stall, but errors in parameters cause us to ignore the command + * and continue processing. + * The process_* functions which handle individual ITS commands all + * return an ItsCmdResult which tells process_cmdq() whether it should + * stall or keep going. + */ +typedef enum ItsCmdResult { + CMD_STALL = 0, + CMD_CONTINUE = 1, +} ItsCmdResult; + static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz) { uint64_t result = 0; @@ -217,8 +234,8 @@ static uint64_t get_dte(GICv3ITSState *s, uint32_t devid, MemTxResult *res) * 3. handling of ITS CLEAR command * 4. handling of ITS DISCARD command */ -static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, - ItsCmdType cmd) +static ItsCmdResult process_its_cmd(GICv3ITSState *s, uint64_t value, + uint32_t offset, ItsCmdType cmd) { AddressSpace *as = &s->gicv3->dma_as; uint32_t devid, eventid; @@ -231,7 +248,7 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, bool ite_valid = false; uint64_t cte = 0; bool cte_valid = false; - bool result = false; + ItsCmdResult result = CMD_STALL; uint64_t rdbase; if (cmd == NONE) { @@ -324,15 +341,15 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, if (cmd == DISCARD) { IteEntry ite = {}; /* remove mapping from interrupt translation table */ - result = update_ite(s, eventid, dte, ite); + result = update_ite(s, eventid, dte, ite) ? CMD_CONTINUE : CMD_STALL; } } return result; } -static bool process_mapti(GICv3ITSState *s, uint64_t value, uint32_t offset, - bool ignore_pInt) +static ItsCmdResult process_mapti(GICv3ITSState *s, uint64_t value, + uint32_t offset, bool ignore_pInt) { AddressSpace *as = &s->gicv3->dma_as; uint32_t devid, eventid; @@ -343,7 +360,7 @@ static bool process_mapti(GICv3ITSState *s, uint64_t value, uint32_t offset, MemTxResult res = MEMTX_OK; uint16_t icid = 0; uint64_t dte = 0; - bool result = false; + ItsCmdResult result = CMD_STALL; devid = ((value & DEVID_MASK) >> DEVID_SHIFT); offset += NUM_BYTES_IN_DW; @@ -404,7 +421,7 @@ static bool process_mapti(GICv3ITSState *s, uint64_t value, uint32_t offset, ite.itel = FIELD_DP64(ite.itel, ITE_L, DOORBELL, INTID_SPURIOUS); ite.iteh = FIELD_DP32(ite.iteh, ITE_H, ICID, icid); - result = update_ite(s, eventid, dte, ite); + result = update_ite(s, eventid, dte, ite) ? CMD_CONTINUE : CMD_STALL; } return result; @@ -472,14 +489,14 @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, bool valid, } } -static bool process_mapc(GICv3ITSState *s, uint32_t offset) +static ItsCmdResult process_mapc(GICv3ITSState *s, uint32_t offset) { AddressSpace *as = &s->gicv3->dma_as; uint16_t icid; uint64_t rdbase; bool valid; MemTxResult res = MEMTX_OK; - bool result = false; + ItsCmdResult result = CMD_STALL; uint64_t value; offset += NUM_BYTES_IN_DW; @@ -509,7 +526,7 @@ static bool process_mapc(GICv3ITSState *s, uint32_t offset) * command in the queue */ } else { - result = update_cte(s, icid, valid, rdbase); + result = update_cte(s, icid, valid, rdbase) ? CMD_CONTINUE : CMD_STALL; } return result; @@ -578,7 +595,8 @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, bool valid, } } -static bool process_mapd(GICv3ITSState *s, uint64_t value, uint32_t offset) +static ItsCmdResult process_mapd(GICv3ITSState *s, uint64_t value, + uint32_t offset) { AddressSpace *as = &s->gicv3->dma_as; uint32_t devid; @@ -586,7 +604,7 @@ static bool process_mapd(GICv3ITSState *s, uint64_t value, uint32_t offset) uint64_t itt_addr; bool valid; MemTxResult res = MEMTX_OK; - bool result = false; + ItsCmdResult result = CMD_STALL; devid = ((value & DEVID_MASK) >> DEVID_SHIFT); @@ -623,7 +641,7 @@ static bool process_mapd(GICv3ITSState *s, uint64_t value, uint32_t offset) * command in the queue */ } else { - result = update_dte(s, devid, valid, size, itt_addr); + result = update_dte(s, devid, valid, size, itt_addr) ? CMD_CONTINUE : CMD_STALL; } return result; @@ -641,7 +659,6 @@ static void process_cmdq(GICv3ITSState *s) uint64_t data; AddressSpace *as = &s->gicv3->dma_as; MemTxResult res = MEMTX_OK; - bool result = true; uint8_t cmd; int i; @@ -668,6 +685,8 @@ static void process_cmdq(GICv3ITSState *s) } while (wr_offset != rd_offset) { + ItsCmdResult result = CMD_CONTINUE; + cq_offset = (rd_offset * GITS_CMDQ_ENTRY_SIZE); data = address_space_ldq_le(as, s->cq.base_addr + cq_offset, MEMTXATTRS_UNSPECIFIED, &res); @@ -726,18 +745,16 @@ static void process_cmdq(GICv3ITSState *s) default: break; } - if (result) { + if (result == CMD_CONTINUE) { rd_offset++; rd_offset %= s->cq.num_entries; s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_offset); } else { - /* - * in this implementation, in case of dma read/write error - * we stall the command processing - */ + /* CMD_STALL */ s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, STALLED, 1); qemu_log_mask(LOG_GUEST_ERROR, - "%s: %x cmd processing failed\n", __func__, cmd); + "%s: 0x%x cmd processing failed, stalling\n", + __func__, cmd); break; } }