From patchwork Mon Dec 20 21:41:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 526099 Delivered-To: patch@linaro.org Received: by 2002:a05:6e04:2287:0:0:0:0 with SMTP id bl7csp4479314imb; Mon, 20 Dec 2021 13:49:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJwNSK1n4ICf1A/fatnLgJtUjDOWgyPha2/c2q1n2UAxe1f/iI9Nd3lWE/kv+QcnzrAKhXqe X-Received: by 2002:a05:6902:1104:: with SMTP id o4mr253286ybu.348.1640036971707; Mon, 20 Dec 2021 13:49:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1640036971; cv=none; d=google.com; s=arc-20160816; b=R79+QECjDndOqyRst5bGCQsQwiJ0d/a99Kg3s0wPQgxVOymm9s+ye1wRkZ66yhxz9G YTDTclmxxqYklZ6pI8FQmXFkv73pnEnDbAkJNFZqDv4pbM0sCTjnvCK5aK+btfE9Z+Od rrxevn0iHhTjrfFDRxE6DOSe46/fBbFr2ANkbZnx+y86oRf20Fir2w8s5VD4rX1GIqKd Hcpv5bjYKrw7DXk4kKWEbs/v40CN56VZTbzhD7h2qXXZuPjf2Fsmui1sfEZRhwVbzKLY cBQvpnF0grWJHFrP7od30bT6p4lFdpdlktOGrtfpqaKr4+pDy6K5tMbuwwS2jtXzUTlT lwfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WQTgDhCLBaZE1Cn7juEE6p/otG9i2OoS7z9LWg/JxZA=; b=NrYB9PMkIgZJq4Ah0dX0Y+o9TLPA/PwnViI8MEoUny8mcgCXXSK1PGEFRGEDAZLlCZ cGb9mHkSopGe9S2KH2p1eDuGmHRlmYB5sMel/UwwESDvfCLGljzcmBUyHlPSKNr192Tt bOOAb0paczC6QPvoFkRNc5YKPJP4uF64KKyAXooUgyq9Wpv0McxMRavc5bMfCFrVLQW8 5Nt+Oml4qEaAL9mIQjRDPDR0cOZu6M3O0icwmo5NF3YbhZNisJyESSTuNOiMO6SHflMw msd+uBNlBNwULxwiwOm2Hf42zAWh8o7iL75gSCpxu0CSEns046+WLS88/oKa8QuRf5U0 ZmoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kTWDf8pY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y205si19871450yby.280.2021.12.20.13.49.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Dec 2021 13:49:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kTWDf8pY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mzQXD-0002Vw-7b for patch@linaro.org; Mon, 20 Dec 2021 16:49:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mzQPi-0000FK-30 for qemu-devel@nongnu.org; Mon, 20 Dec 2021 16:41:46 -0500 Received: from [2607:f8b0:4864:20::631] (port=33490 helo=mail-pl1-x631.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mzQPg-0002z1-8T for qemu-devel@nongnu.org; Mon, 20 Dec 2021 16:41:45 -0500 Received: by mail-pl1-x631.google.com with SMTP id y7so9134989plp.0 for ; Mon, 20 Dec 2021 13:41:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WQTgDhCLBaZE1Cn7juEE6p/otG9i2OoS7z9LWg/JxZA=; b=kTWDf8pY2nkeoALc69mYRaE2QPKi7TmXoJIKDUTJUv8xI0lSxz5MQXpL9Prfpibo6s 6x95Lwqp66yyCJQi7+p4ksQMOHCMmH5g6q5Fm/9WinxBsQ/kE4Et70dFDpqtG1+qgLtS RIi6laYyIoJIX33lz49f7uxdYKrasmicdxVHGTAPAr/MwnBopIU1kSouyzwmHrwnfDMm gjIEfy80b5J63fphsohV/yUcEv7SyMx00Mr/2seAc14M3mHsZl6MCFDEkSI9aiP19tax ArwbW4Mb1SU4vEZDvA8uEZBUmNLojnIl+GIwKNGKEdf/fKYdr63kY6Ddq4yMHYOun3dw OfQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WQTgDhCLBaZE1Cn7juEE6p/otG9i2OoS7z9LWg/JxZA=; b=eS8Buj8XSiwU794r7g0PY3roJHKMswwdUUE8VhZk2kOhJT+pFLIRb60m+wwtXFOPn5 36JyGrvdsROZm60qaWNpBcT/L3Q7e2g1Hva5dEp8ZeiyXayr2ATWh4yVscgaodFzBuJQ 1KAWhij3qWqRKNqSvqYNqM6lqEjAxfUauWLfJ1Ue1GXOhGdIM3xp8S9ltt4FWs4NrYv6 /31qYiEUPrKxlCW/YA2Mr/n5fbA6yPtwactfmTN+YZgH/3Mp+78IbKo7dxFEmDQCf80s XU6utAg7d++A2FSiymhCh6HmQzo2MsuBvrMFmSty+37O3o/FOaNp0+omQWNdmCbUIwFq KJfA== X-Gm-Message-State: AOAM53221hcibR4kltslpAI/nPg58kIfqiNnHUbI29OM5pfzKM1LT/j0 m5700lEUQuImzQuao4Zs4nmmqTFzuzBP+g== X-Received: by 2002:a17:90b:798:: with SMTP id l24mr190746pjz.122.1640036502522; Mon, 20 Dec 2021 13:41:42 -0800 (PST) Received: from localhost.localdomain ([156.19.246.20]) by smtp.gmail.com with ESMTPSA id u10sm12508748pfm.58.2021.12.20.13.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 13:41:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/6] target/alpha: Implement prctl_unalign_sigbus Date: Mon, 20 Dec 2021 13:41:33 -0800 Message-Id: <20211220214135.189157-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220214135.189157-1-richard.henderson@linaro.org> References: <20211220214135.189157-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::631 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- linux-user/alpha/target_prctl.h | 2 +- target/alpha/cpu.h | 5 +++++ target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 10 deletions(-) diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h index eb53b31ad5..5629ddbf39 100644 --- a/linux-user/alpha/target_prctl.h +++ b/linux-user/alpha/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index afd975c878..e819211503 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,6 +383,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; @@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *pflags = env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #ifdef CONFIG_USER_ONLY diff --git a/target/alpha/translate.c b/target/alpha/translate.c index a4c3f43e72..208ae5fbd5 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp = tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |= UNALIGN(ctx); } dest = ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) { TCGv tmp = tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |= UNALIGN(ctx); } src = load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) #ifdef CONFIG_USER_ONLY ctx->ir = cpu_std_ir; + ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->palbr = env->palbr; ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir);