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[37.14.164.149]) by smtp.gmail.com with ESMTPSA id m21sm16311280wrb.2.2021.11.30.02.37.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Nov 2021 02:37:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/3] target/m68k: Implement TRAPV Date: Tue, 30 Nov 2021 11:37:50 +0100 Message-Id: <20211130103752.72099-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130103752.72099-1-richard.henderson@linaro.org> References: <20211130103752.72099-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::332 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- target/m68k/translate.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index af43c8eab8..858ba761fc 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4863,6 +4863,22 @@ DISAS_INSN(trap) gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf)); } +static void do_trapcc(DisasContext *s, int cond) +{ + TCGLabel *over = gen_new_label(); + + /* Jump over if !cond. */ + gen_jmpcc(s, cond ^ 1, over); + + gen_exception(s, s->base.pc_next, EXCP_TRAPCC); + gen_set_label(over); +} + +DISAS_INSN(trapv) +{ + do_trapcc(s, 9); /* VS */ +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6026,6 +6042,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(trapv, 4e76, ffff, M68000); INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0);