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[209.51.188.17]) by mx.google.com with ESMTPS id a12si2609772vko.289.2021.11.25.07.45.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Nov 2021 07:45:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jxmiqGMc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGw0-0003f2-9y for patch@linaro.org; Thu, 25 Nov 2021 10:45:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGsh-0006Vq-SV for qemu-devel@nongnu.org; Thu, 25 Nov 2021 10:41:51 -0500 Received: from [2a00:1450:4864:20::42d] (port=43590 helo=mail-wr1-x42d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGse-0002Im-O6 for qemu-devel@nongnu.org; Thu, 25 Nov 2021 10:41:51 -0500 Received: by mail-wr1-x42d.google.com with SMTP id v11so12490748wrw.10 for ; Thu, 25 Nov 2021 07:41:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WGre360ECFC32is5bfbd0HWJa+SsjO4LmCB6eMj0auw=; b=jxmiqGMcrHKS3U+aDn3SAqkaNB0VXkUzfOIIhSXXmOt/dh2CNY6JmiHRmB45kTFepQ 9Nncig4wIHBZ0yqpiIomLWHAGGYqjEUw6+1OBSCNbWt6d8le6uNm+ygMy5jAk0jM/euO in/FbB+flrzYeCpCs6Jok24b46GwJe0HNi7V4quJdgfkh0hsIaeQqyBKq3gUoTdw0yNF 76/Kvhhy5O68fmhkEgPhotQ7XyKKFQ4l4lBkEixKxMJ5D4Qf+dugiY9sh7tGlOLgNJY2 5FvD9ygFxNNrFV15805VZ/gwTNv9Cn9am0Po5peQsd7wwlLQQVFJM/yuyEzHz4gbc3BR K/Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WGre360ECFC32is5bfbd0HWJa+SsjO4LmCB6eMj0auw=; b=78KlToGsSaRt1KvaGH8pkrR689qXbbvhT8M4JQMQRCQf3XlYT35X/3rOrAYtTiR5oy ILaLkGoBifTJ/KTFaBavh168LaVt6sO3qTYqbv19WZwC2qKR4p5sw2m1ANZfbIpTp6pY CPpVNjWhdDgcDg8jzhpHm/Wm7ZWisJWjfjU0IABgPEYW5lGfaXKzKHatqNCgZyej3Dc0 t06Pw3fFqnbLb2eryZFwPhJMckd8N6K3ZxhKHp5HPRXQcyhekJTTOnMzo6vnY/DwN67c Y8JLkwWhXziaSMMrPgOr3uFZFny0LXWV8niqC0TFpr8KNaHbX9oKeQiSHKr2ZiK4RQWH 4rTQ== X-Gm-Message-State: AOAM531KjIeYUjUn5kyLkj+nC9NjZGkJ3MPvgZ+xdQKU6PXfOUvUC3uX AReIFwiLB5ULCIjlHf1zj4Aieg== X-Received: by 2002:a5d:456e:: with SMTP id a14mr7572748wrc.256.1637854906790; Thu, 25 Nov 2021 07:41:46 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id d6sm3235869wrn.53.2021.11.25.07.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:41:45 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2699A1FF99; Thu, 25 Nov 2021 15:41:45 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v2 2/7] accel/tcg: suppress IRQ check for special TBs Date: Thu, 25 Nov 2021 15:41:39 +0000 Message-Id: <20211125154144.2904741-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211125154144.2904741-1-alex.bennee@linaro.org> References: <20211125154144.2904741-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, berrange@redhat.com, David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , f4bug@amsat.org, Peter Xu , stefanha@redhat.com, crosa@redhat.com, pbonzini@redhat.com, Pavel Dovgalyuk , =?utf-8?q?Alex_Benn=C3=A9e?= , aurelien@aurel32.net Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When we set cpu->cflags_next_tb it is because we want to carefully control the execution of the next TB. Currently there is a race that causes the second stage of watchpoint handling to get ignored if an IRQ is processed before we finish executing the instruction that triggers the watchpoint. Use the new CF_NOIRQ facility to avoid the race. We also suppress IRQs when handling precise self modifying code to avoid unnecessary bouncing. Signed-off-by: Alex Bennée Cc: Pavel Dovgalyuk Fixes: https://gitlab.com/qemu-project/qemu/-/issues/245 --- v2 - split the CF_NOIRQ implementation - only apply CF_NOIRQ for watchpoints/SMC handling - minor reword of commit --- accel/tcg/cpu-exec.c | 9 +++++++++ accel/tcg/translate-all.c | 2 +- softmmu/physmem.c | 2 +- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2d14d02f6c..409ec8c38c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -721,6 +721,15 @@ static inline bool need_replay_interrupt(int interrupt_request) static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { + /* + * If we have requested custom cflags with CF_NOIRQ we should + * skip checking here. Any pending interrupts will get picked up + * by the next TB we execute under normal cflags. + */ + if (cpu->cflags_next_tb != -1 && cpu->cflags_next_tb & CF_NOIRQ) { + return false; + } + /* Clear the interrupt flag now since we're processing * cpu->interrupt_request and cpu->exit_request. * Ensure zeroing happens before reading cpu->exit_request or diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bd0bb81d08..1cd06572de 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1738,7 +1738,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (current_tb_modified) { page_collection_unlock(pages); /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(cpu); + cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); } diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 314f8b439c..b43f92e900 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -946,7 +946,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, cpu_loop_exit(cpu); } else { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | CF_LAST_IO | curr_cflags(cpu); + cpu->cflags_next_tb = 1 | CF_LAST_IO | CF_NOIRQ | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); }