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[37.158.79.165]) by smtp.gmail.com with ESMTPSA id q84sm14044877wme.3.2021.11.19.08.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 08:05:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/35] softfloat: Add flags specific to Inf / Inf and 0 / 0 Date: Fri, 19 Nov 2021 17:04:31 +0100 Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211119160502.17432-1-richard.henderson@linaro.org> References: <20211119160502.17432-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, alex.bennee@linaro.org, clg@kaod.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" PowerPC has these flags, and it's easier to compute them here than after the fact. Signed-off-by: Richard Henderson --- include/fpu/softfloat-types.h | 2 ++ fpu/softfloat-parts.c.inc | 16 +++++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 56b4cf7835..5a9671e564 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -154,6 +154,8 @@ enum { float_flag_output_denormal = 0x0040, float_flag_invalid_isi = 0x0080, /* inf - inf */ float_flag_invalid_imz = 0x0100, /* inf * 0 */ + float_flag_invalid_idi = 0x0200, /* inf / inf */ + float_flag_invalid_zdz = 0x0400, /* 0 / 0 */ }; /* diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3ed793347b..b8563cd2df 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -590,11 +590,13 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, } /* 0/0 or Inf/Inf => NaN */ - if (unlikely(ab_mask == float_cmask_zero) || - unlikely(ab_mask == float_cmask_inf)) { - float_raise(float_flag_invalid, s); - parts_default_nan(a, s); - return a; + if (unlikely(ab_mask == float_cmask_zero)) { + float_raise(float_flag_invalid | float_flag_invalid_zdz, s); + goto d_nan; + } + if (unlikely(ab_mask == float_cmask_inf)) { + float_raise(float_flag_invalid | float_flag_invalid_idi, s); + goto d_nan; } /* All the NaN cases */ @@ -625,6 +627,10 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_divbyzero, s); a->cls = float_class_inf; return a; + + d_nan: + parts_default_nan(a, s); + return a; } /*