From patchwork Thu Oct 21 21:05:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516072 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp328968imj; Thu, 21 Oct 2021 14:12:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfNolc1BPdWxN6yzCuv7BLW1Atx4YsNukq8Koh6/CyWCtiShO/owMo9GJl/lWbM3zTxjS1 X-Received: by 2002:a4a:d6c7:: with SMTP id j7mr6290851oot.36.1634850722353; Thu, 21 Oct 2021 14:12:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850722; cv=none; d=google.com; s=arc-20160816; b=Z6v00JO0VLPmiQSvPqPXgw7BrpxecQ46YRUa1yx1HhnT7+ZeoFzj0i/TaOwxk4xfhB pJD2W3+p7tboNma50/l61zzFwaGefeUuGmTFJBAM0lQj/22ysB1i9da2FOhDsiChMrkt vsul0bHk7rM/dhKFD0uXkZfKmwhedj8qAFdR90I8j2S6kAHJxhtIC58Ne5tjOvHdZBQ9 NWa+xpp4qsYSAIouQ/pcXVrEE5NvqkN6XgwA8rvKZ+PY2S46BOHc/Mj2ifzppZs1icsE 9BiP1B9dIx9XMChBf0uN90W7Gh6o2kvTjd+UgkSucIMNrs8CfUocTTekShALdJpLOnkk r3rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VL2DZVHiwEan+Uudq/w6Cd72DWHAAD7YXIJuDWEUvWk=; b=DTa/t5LJAsFoH7Wn65QboFuhBO34k7RtPpcm5/UnMaONOSBntxQHAQ/GMieRTusjQ4 8kAT//PdmQO0PmzMHfaTQe/ZRLgLxtYPwVElagEAjmJUfoW1lFubkMi8dXyonGWR4+gQ V+PpPs2p5c6ZYhpCAO+/AcDkAZH/33Ig95Xt4j135beP+O2s0oFw7VvrPyH5V5d6JKn3 GP5BYx0DX62L/9Xh1vXrSOdofie1Kog1nJvADof8PMZvnwYaN+rihowErB40HrIFu98m 8A2E7TOKDY5kzSrHjKCJNZfkdJIHWCc6FUc8OIzxfifZXeFFTe2P6DsMVGuHmjobLR8a 1rfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Mi7Hb9WF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v9si7183719oig.137.2021.10.21.14.12.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:12:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Mi7Hb9WF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfM1-0005Bv-L4 for patch@linaro.org; Thu, 21 Oct 2021 17:12:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfGA-0007P7-CM for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:58 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:36667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfG5-0004Hm-00 for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:57 -0400 Received: by mail-pf1-x42c.google.com with SMTP id m26so1766813pff.3 for ; Thu, 21 Oct 2021 14:05:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VL2DZVHiwEan+Uudq/w6Cd72DWHAAD7YXIJuDWEUvWk=; b=Mi7Hb9WFzjWVnjXdzRPzOGm8jcuK8ogbIT4yFavzYnOEu2FJy2/nk6SERA7vqorRln EIRxLT263wbxs8XOFgkV08nK9q/5CjU9E4p7xDCrMjCUfUq50ZsTDRZlRDTYU4OKh0Uy Ryx0+9NVyAY4sulegLh7XhFJqIi6wcTKvbHCVFWOgLftUykCOkGVBElVhMHVmPd+AxlF f0pt5x3wW1yGFXihVZZNTYIB1xmoIsnTIYByti0B7T4F/C6FHsTW5oEFCdC2OX3tEUrX cYZIsyoKvAoH0QLcuDpXZZBSd0pf9ii0C9RbIfe8LxHs0Rf0/6qDQC0jzuVKGu3jt5/b uWqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VL2DZVHiwEan+Uudq/w6Cd72DWHAAD7YXIJuDWEUvWk=; b=hzbAZjznnpeYHeqsvkGlPfHIA/3tWQHVRaHKnVznlmJaNfKINducpbs6FKY6ou1RQm 6kkHcixwC9kf09Sq0WZIKJ5r1G/S1zrT+3Uqa6j1D5BuPfj9gPhLfnKnAGgiMdXxOCmx 7GEph1uS2VGZuOHirtFyKzux8v5onXrKIiVqRKfm2/mqF5U8kg8lAF3Cl1aqP1zHHQqv CbQbLiXhE8dk5hHvjBXwLQLF2b//LtruzaIqyXQkPId/WHgNYL2HH1u5QEB/X0A99H/f SaGDi42otQ4bLTb9bHnxiWMZTT8XsTiKrRoHSolokIH96CjgWGdmxyBRiqPbNL8JKkkE m4rw== X-Gm-Message-State: AOAM5303SE26p0FiV6xCAxBk4qx9+DWpYrFMPDPDk76LxIvMGXK9V4Lt Jvebczap7RwgUQUeR2M2Y2TGp2Kq9Xfklw== X-Received: by 2002:a05:6a00:a8b:b0:44d:ef7c:94b9 with SMTP id b11-20020a056a000a8b00b0044def7c94b9mr7979448pfl.36.1634850351625; Thu, 21 Oct 2021 14:05:51 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g7sm5981670pgp.17.2021.10.21.14.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:05:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/48] tcg/optimize: Split out fold_const{1,2} Date: Thu, 21 Oct 2021 14:05:06 -0700 Message-Id: <20211021210539.825582-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a whole bunch of placeholder functions, which are currently identical. That won't last as more code gets moved. Use CASE_32_64_VEC for some logical operators that previously missed the addition of vectors. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 254 +++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 202 insertions(+), 52 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 159a5a9ee5..e66d935808 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -660,6 +660,60 @@ static void finish_folding(OptContext *ctx, TCGOp *op) } } +/* + * The fold_* functions return true when processing is complete, + * usually by folding the operation to a constant or to a copy, + * and calling tcg_opt_gen_{mov,movi}. They may do other things, + * like collect information about the value produced, for use in + * optimizing a subsequent operation. + * + * These first fold_* functions are all helpers, used by other + * folders for more specific operations. + */ + +static bool fold_const1(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1])) { + uint64_t t; + + t = arg_info(op->args[1])->val; + t = do_constant_folding(op->opc, t, 0); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + return false; +} + +static bool fold_const2(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + uint64_t t1 = arg_info(op->args[1])->val; + uint64_t t2 = arg_info(op->args[2])->val; + + t1 = do_constant_folding(op->opc, t1, t2); + return tcg_opt_gen_movi(ctx, op, op->args[0], t1); + } + return false; +} + +/* + * These outermost fold_ functions are sorted alphabetically. + */ + +static bool fold_add(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_and(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_andc(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + static bool fold_call(OptContext *ctx, TCGOp *op) { TCGContext *s = ctx->tcg; @@ -692,6 +746,26 @@ static bool fold_call(OptContext *ctx, TCGOp *op) return true; } +static bool fold_ctpop(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_eqv(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_exts(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_extu(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + static bool fold_mb(OptContext *ctx, TCGOp *op) { /* Eliminate duplicate and redundant fence instructions. */ @@ -716,6 +790,41 @@ static bool fold_mb(OptContext *ctx, TCGOp *op) return true; } +static bool fold_multiply(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_nand(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_neg(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_nor(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_not(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_or(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_orc(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) { /* Opcodes that touch guest memory stop the mb optimization. */ @@ -730,6 +839,21 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op) return false; } +static bool fold_shift(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_sub(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_xor(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { @@ -1276,26 +1400,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(not): - CASE_OP_32_64(neg): - CASE_OP_32_64(ext8s): - CASE_OP_32_64(ext8u): - CASE_OP_32_64(ext16s): - CASE_OP_32_64(ext16u): - CASE_OP_32_64(ctpop): - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - if (arg_is_const(op->args[1])) { - tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - CASE_OP_32_64(bswap16): CASE_OP_32_64(bswap32): case INDEX_op_bswap64_i64: @@ -1307,36 +1411,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(add): - CASE_OP_32_64(sub): - CASE_OP_32_64(mul): - CASE_OP_32_64(or): - CASE_OP_32_64(and): - CASE_OP_32_64(xor): - CASE_OP_32_64(shl): - CASE_OP_32_64(shr): - CASE_OP_32_64(sar): - CASE_OP_32_64(rotl): - CASE_OP_32_64(rotr): - CASE_OP_32_64(andc): - CASE_OP_32_64(orc): - CASE_OP_32_64(eqv): - CASE_OP_32_64(nand): - CASE_OP_32_64(nor): - CASE_OP_32_64(muluh): - CASE_OP_32_64(mulsh): - CASE_OP_32_64(div): - CASE_OP_32_64(divu): - CASE_OP_32_64(rem): - CASE_OP_32_64(remu): - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tmp = do_constant_folding(opc, arg_info(op->args[1])->val, - arg_info(op->args[2])->val); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - CASE_OP_32_64(clz): CASE_OP_32_64(ctz): if (arg_is_const(op->args[1])) { @@ -1637,9 +1711,71 @@ void tcg_optimize(TCGContext *s) } break; + default: + break; + + /* ---------------------------------------------------------- */ + /* Sorted alphabetically by opcode as much as possible. */ + + CASE_OP_32_64_VEC(add): + done = fold_add(&ctx, op); + break; + CASE_OP_32_64_VEC(and): + done = fold_and(&ctx, op); + break; + CASE_OP_32_64_VEC(andc): + done = fold_andc(&ctx, op); + break; + CASE_OP_32_64(ctpop): + done = fold_ctpop(&ctx, op); + break; + CASE_OP_32_64(div): + CASE_OP_32_64(divu): + done = fold_const2(&ctx, op); + break; + CASE_OP_32_64(eqv): + done = fold_eqv(&ctx, op); + break; + CASE_OP_32_64(ext8s): + CASE_OP_32_64(ext16s): + case INDEX_op_ext32s_i64: + case INDEX_op_ext_i32_i64: + done = fold_exts(&ctx, op); + break; + CASE_OP_32_64(ext8u): + CASE_OP_32_64(ext16u): + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + done = fold_extu(&ctx, op); + break; case INDEX_op_mb: done = fold_mb(&ctx, op); break; + CASE_OP_32_64(mul): + CASE_OP_32_64(mulsh): + CASE_OP_32_64(muluh): + done = fold_multiply(&ctx, op); + break; + CASE_OP_32_64(nand): + done = fold_nand(&ctx, op); + break; + CASE_OP_32_64(neg): + done = fold_neg(&ctx, op); + break; + CASE_OP_32_64(nor): + done = fold_nor(&ctx, op); + break; + CASE_OP_32_64_VEC(not): + done = fold_not(&ctx, op); + break; + CASE_OP_32_64_VEC(or): + done = fold_or(&ctx, op); + break; + CASE_OP_32_64_VEC(orc): + done = fold_orc(&ctx, op); + break; case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: done = fold_qemu_ld(&ctx, op); @@ -1649,8 +1785,22 @@ void tcg_optimize(TCGContext *s) case INDEX_op_qemu_st_i64: done = fold_qemu_st(&ctx, op); break; - - default: + CASE_OP_32_64(rem): + CASE_OP_32_64(remu): + done = fold_const2(&ctx, op); + break; + CASE_OP_32_64(rotl): + CASE_OP_32_64(rotr): + CASE_OP_32_64(sar): + CASE_OP_32_64(shl): + CASE_OP_32_64(shr): + done = fold_shift(&ctx, op); + break; + CASE_OP_32_64_VEC(sub): + done = fold_sub(&ctx, op); + break; + CASE_OP_32_64_VEC(xor): + done = fold_xor(&ctx, op); break; }