From patchwork Tue Oct 19 15:24:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515976 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp851550imp; Tue, 19 Oct 2021 09:53:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyzTR6qrc04Dk/6cUKFr7ZziFVtRGnCLSFJpVf0FA/CPGQckOESIdntcGozd0sBpe5z6IAe X-Received: by 2002:a05:6102:160b:: with SMTP id cu11mr21753821vsb.45.1634662413442; Tue, 19 Oct 2021 09:53:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634662413; cv=none; d=google.com; s=arc-20160816; b=D0CH9SxZyhrAibUW2ZNgTi4ixHiUDihSEDOq5LiWCP8AMTA4Uqqme78f2KvYmEDH/e IIi2jB7bSIg7L/TVzFQNBd8W89eFnWNbbaF4ji6o1cfsildt0E5T3dmaPgP5XblpCgjk ps9tpBp139qezUwp3wx53Csc8W08hRyDAjqqyuIYNIpnzTaRKGSWNLRdAqJoPlqmijFa 5zaviPUGJOO/ItfqS6lFT7PkTPqIU9oGgQqiAnvOu+D6eUYWs2RN/5cj8bCBSAVgH5hl Z6tZz37yrhpjx3JA8HqPNwjjjrlMQ67TF10yqMIpQsR6xIcdqQLElZh/tvx+GbttK9Rr NS6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=SVkXmoicccK7YMbpMaBfa/m1mph23F93g509+R/Zgu7DIKaTWQIKU1Qcm/2tdaiA00 K5AWUQmwzevAqmBeIiWaV7StGsE0bQ0W2ucY/cDfABU9KHHmfgqPR6SK6jCSxM3VMhJJ WMZqF4WJNxgqboAtSzAqakNfpov02Zlz/Ok8fLyUm7X7lkLFodTnlRsJPlbBW2UXwRnd zVyeF5ngRjwlBho5ObfAGIh64qzrY3goCXJTGB8mr9WN9sjNjNRM0PUACDM+vfbtJ8/K MoYUtqbzsARnTOtHkTQHTbjH7Gkl4TKe8SNH/EktrpFQ0KJ2zrodxIxuC8ZBLCc3JrW/ bhnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vpE4vK8n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o1si16307426vsl.356.2021.10.19.09.53.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 09:53:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vpE4vK8n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcsMm-0005BX-Pd for patch@linaro.org; Tue, 19 Oct 2021 12:53:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqz7-0005TV-F3 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:01 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:33358) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcqyy-0007dN-3h for qemu-devel@nongnu.org; Tue, 19 Oct 2021 11:25:01 -0400 Received: by mail-pl1-x630.google.com with SMTP id y4so13943811plb.0 for ; Tue, 19 Oct 2021 08:24:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=vpE4vK8nDInCQ0L8wI/0xkgse3rPkmAu0lHL8TcdPqJQG66Y7jAOfx3akoUymzK3y7 Ew1QtUXp8FaeYmtDED62F4fodajz/p1ZsCHOiH7DovMX0U1qWoIFhWIf2TzSmBj3JanH eis0J5MyCi86EFtEFDt2elhgQIz+GZ0PEiy9fYuqAFqeAfXOFTYozoZK0G8mC6Db/1J7 h6NLV8nMpJtdiB11d/xK0djDdJKQg7EBD3KfbUG0Ar52JvSPe0TbceBYqvuo/Efigxfi 2VzuG3/Mue8GDPR0D4Bu/XxCj48GilMu+6CEno6BUhU5QFvn8aySjA9BF9O00oFG7Q6K N2/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=mHmUWmzZaGW1QwzbgYRWjAJdytYSZjli/BJR8HzlRmxMauRAD74gdSLQj55TYqMmnN eBLoNzFh4dkGNFviZbsOSi7znAlqVlQ086BqDKtqVlas/nG8c25l54oNaW0achbJ+Dym pgx9OUHMNbPlQWx7w3xu92aAOx/9P3cU2/+ljMLBvQ0EWlOYSdSZ/YLaiuwcnPQMIa3B iqn5g6Ger3/bdAVNvox+xtmsa14X5pvgVKN8rCPoNV1K4Hq8ljtlgs1lE8b5tgPwO8O0 3cP1Pl3Xl0lcZwS/qe7HGQJpO8wKi9dFuIMfm/3UTuelbNbwBZTOK9aenjEp/CxE7MO7 1msA== X-Gm-Message-State: AOAM531KqmFhNZ8mSuxSKRekZUWlMS8zeL75+eBEBiHpQAWEavvC5d9t zHWm01YYTePVO6tHxgc4L68aMfnMzOI= X-Received: by 2002:a17:90a:f2c2:: with SMTP id gt2mr551670pjb.2.1634657090576; Tue, 19 Oct 2021 08:24:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i2sm3293814pjt.19.2021.10.19.08.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 08:24:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 16/16] target/riscv: Compute mstatus.sd on demand Date: Tue, 19 Oct 2021 08:24:38 -0700 Message-Id: <20211019152438.269077-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019152438.269077-1-richard.henderson@linaro.org> References: <20211019152438.269077-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The position of this read-only field is dependent on the current cpu width. Rather than having to compute that difference in many places, compute it only on read. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 37 ++++++++++++++++++++++--------------- target/riscv/translate.c | 5 ++--- 3 files changed, 25 insertions(+), 20 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 429afd1f48..0d1132f39d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -185,10 +185,9 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL | sd; + MSTATUS64_UXL; bool current_virt = riscv_cpu_virt_enabled(env); g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c4a479ddd2..69e4d65fcd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -477,10 +477,28 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno, } /* Machine Trap Setup */ + +/* We do not store SD explicitly, only compute it on demand. */ +static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) +{ + if ((status & MSTATUS_FS) == MSTATUS_FS || + (status & MSTATUS_XS) == MSTATUS_XS) { + switch (xl) { + case MXL_RV32: + return status | MSTATUS32_SD; + case MXL_RV64: + return status | MSTATUS64_SD; + default: + g_assert_not_reached(); + } + } + return status; +} + static RISCVException read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mstatus; + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); return RISCV_EXCP_NONE; } @@ -498,7 +516,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, { uint64_t mstatus = env->mstatus; uint64_t mask = 0; - int dirty; /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | @@ -520,12 +537,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = (mstatus & ~mask) | (val & mask); - dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | - ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mstatus = set_field(mstatus, MSTATUS32_SD, dirty); - } else { - mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + if (riscv_cpu_mxl(env) == MXL_RV64) { /* SXL and UXL fields are for now read only */ mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); @@ -798,13 +810,8 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mask |= SSTATUS32_SD; - } else { - mask |= SSTATUS64_SD; - } - - *val = env->mstatus & mask; + /* TODO: Use SXL not MXL. */ + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index de013fbf9b..35245aafa7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -288,7 +287,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_temp_free(tmp); } @@ -299,7 +298,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_temp_free(tmp); }