From patchwork Tue Oct 19 00:00:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515937 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp70586imp; Mon, 18 Oct 2021 17:06:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwisTiKFim8dyZRnIRCEBulSMpLbFjbRBx2q8hV9dhFmo1eWoY7BeteA6/RD74qhywYxhRv X-Received: by 2002:a05:6102:c0d:: with SMTP id x13mr9896473vss.54.1634602009655; Mon, 18 Oct 2021 17:06:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602009; cv=none; d=google.com; s=arc-20160816; b=jENZS3NaU2bHKvcsdWr5ZSnhOCqCxRP6p97WX4twY8B3ExSjohW14XKTH3gwdqvnxs jQKlGrDxrcpwc80TfnhlnsyVtHVFoOm5MDLFyrKglyXDMb86vAaM5fB14ePClr4huShQ eONxV1BKDwiwvu+5Vdaxbsq/FszbuoBQW5kxdWSE1wCpEyfgvRX+hfH60VdGUJgAnywh rOceGGOgwCXf4wODpyIxZfYl2peCYL64VXoV8QuU1Zv0MKct8zI8L/mRT50wwcC+Orol f9+jJOLCdeDXd+xl6eUio4NY6vJYqQeImVIyyYz/xN8qJRnPrjSiJZzafUSwRCxkpmDt v7eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=Bipwhp9Krm16LjUeGkPwJ8Um9jNSSpBwGWGDLBu3HIhBo7nspBi1aYdHH51HDYrd71 0AsmlGf992YoXl6oR4k9gUQ7xiWuV+vLbizl3v6ZFy3W1UvoXCp4/nvMkVawQx/1u4Ks 2z1w1HX5KGpPk/uGX2iGDfHtsiV4zLNpZ5M2o8DrL9UNO6Q9ynd2IWegnHQK06GnB4an +XcTqMutMi6XjS0ib7fNWYIVC1uLYXUg8DLQ4gfUpjuE5JAxC3y8WJ4sLsPsvMNzAO7o LYDkr3ewp26lIsrc79bkSSQDIH4gpVRRhG877eOiGpvkXsyOlS+2G/GFMXtNHAidKJbz gckQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lw+0xg2B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j13si4600339vkd.65.2021.10.18.17.06.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:06:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lw+0xg2B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcceX-0002cp-02 for patch@linaro.org; Mon, 18 Oct 2021 20:06:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZB-0004cq-FD for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:17 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:44974) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZ5-0001c1-Ld for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:16 -0400 Received: by mail-pj1-x1036.google.com with SMTP id oa12-20020a17090b1bcc00b0019f715462a8so1248284pjb.3 for ; Mon, 18 Oct 2021 17:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=Lw+0xg2BsoNfCVm3hNJS+cG2SBZjjs3TAxsdAXW1unLolldclQTMvVzXB7lhO+x587 zN4iCH1Xu1Cd+mnY86hukVpNLYwQKXZDy879SQdZVA/kq33U9X4H4H7xkxBlUeHLMMF5 BMioFc8dHY/DS8OrPd14jm/w6ubKHi6658p7rRLXkXXFa/BLo7Vf1nXZumAwIghiSyJI +YW2ldDOEJZFv/tVphPsIrKAdSGUWhAS+XlULINftazRmoKyoPb78AXxyOC3WgxlxRrH 2LjayybZwtiJ1Ug/5MDUYCQ8Vi/rAU90ztSE/PLDY+8FF+uDYajmG+iKC4WYpIoYveuN fCMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=miKLNP6ws8+oDR/KjB6B+5NU/vXf/9MnC7iAElEPbkqDEAe7nqeSHmMXFTH/6cjZDt VCHk+2+Q/xMBKEPy+0+WnqE8xci4ayuoHrBZxlJ47mIX/fOiz4+amgur9sMEpbiAI5ei 9wKFvdK7VS/fZa1aXblHGQJLYmMRNm+AgSIfoIVj1m0sl1Pjiw2NYdlHEpcPaDbT9r02 DKu1PeeDRK1a99zHQZObd129Fhd+XCzmzn3BxqmjetOHe1Y9ba5fjWi/6Wt62EYtvglT NuLKFW/sQ2QOQ/nuMrjR8sGhC7FJ0rMpg0+o9B+DWw5lI4bclXopCMdLGnJmEALAEDe9 fexw== X-Gm-Message-State: AOAM533N99TuEo6XONqkE76OcPWndXuRBMmZd7nyZc9u5mQPwN+Gw+8i ymXjPcNtYir9rr2g1+8ATj2X0U1pKW0= X-Received: by 2002:a17:902:7616:b0:13f:354a:114f with SMTP id k22-20020a170902761600b0013f354a114fmr31104803pll.8.1634601670165; Mon, 18 Oct 2021 17:01:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Date: Mon, 18 Oct 2021 17:00:53 -0700 Message-Id: <20211019000108.3678724-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to cpu_helper.c, as it is large and growing. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 47 ++------------------------------------- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..7084efc452 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc; - *cs_base = 0; - - if (riscv_has_ext(env, RVV)) { - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; -#else - flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; - } - - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..14d1d3cb72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc; + *cs_base = 0; + + if (riscv_has_ext(env, RVV)) { + uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vtype, VTYPE, VILL)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + flags |= TB_FLAGS_MSTATUS_FS; +#else + flags |= cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + flags |= env->mstatus & MSTATUS_FS; + } + + if (riscv_has_ext(env, RVH)) { + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, + get_field(env->mstatus_hs, MSTATUS_FS)); + } +#endif + + *pflags = flags; +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) {