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[209.51.188.17]) by mx.google.com with ESMTPS id w17si8848083jad.34.2021.10.14.21.12.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:12:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=stISHxdx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEZv-0006jz-W0 for patch@linaro.org; Fri, 15 Oct 2021 00:12:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYg-0006h4-7G for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:02 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:33775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYd-00007Y-Vy for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:01 -0400 Received: by mail-pl1-x636.google.com with SMTP id y4so5636522plb.0 for ; Thu, 14 Oct 2021 21:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oOQU7Pbw0+lekQo/Dc4xCn9/9dfAsnRnEEjuG278GdE=; b=stISHxdxUYcJ+m/mrW/EMrcZISPQEdhH2XWaDecY0jEO20NKcvrdgzQb1UPvD0aouY ZgtEy5wmVv32wGXJUro7lcJYO5NfsXjO+Z0jmjNlK/MHYKq05c++dtZTC6MTZK4khnVB woMC8jAUSyQqiyZKWSVfHy5ddy+PCaTv46nIoQlGgJkcChCDPGUnoH+FAsQv+4w8kVFx BUCCN5GebAenGUvR8mLa8KsTQBTTmzUZE0S3dYSRVQ8dCJVWuzqvihKUOlf8X+iR6Q3R A9Gm6bHYWHN/KIdw2tb65R3NIH0FU7ZaBg5k5sa/wEPRu71u+dIZ0BB8O/mWDfaLznZN 7h7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oOQU7Pbw0+lekQo/Dc4xCn9/9dfAsnRnEEjuG278GdE=; b=odd3epmrTSJWelk3XRPSpzu2EPjuaXR77nrnYpc7Hhdk7UAaGLHXcNQO33PVdcwH6c N5ZIGzV+eAu6ZKPjvbEq7DIj85vL0FFBWW/thNkKt2UeFwY96QWXPYA+NWwanMKvMD1s OyNTEURyAlmbSHn28H/7GCWLH3T5k3Scob950l8k/ocYZzLqAdQEdSvZsZguhvznrBmj CCPHL+sXH0Ao2r6/kOl+9xLLenCLq3Qw0+yVSgJTClm6NTiYRdiJVJYLIEmeIB7S6FYl Ka7CSmyiEmBSvd1Qg0/l3/dkEPB1O2cCDWX6omHyuIVQelyKmFeyBaoBO3fHuBDVxYnh gZvg== X-Gm-Message-State: AOAM530xeDDEYnF39tqqWJwSmcf4aFSoL7iPMERW0zjcgji2NrdmGqmA 9vvp3MX+sDV7kdP/L7S25TRpTSODpDNcFA== X-Received: by 2002:a17:90b:4b46:: with SMTP id mi6mr10276124pjb.161.1634271058598; Thu, 14 Oct 2021 21:10:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:10:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures Date: Thu, 14 Oct 2021 21:09:51 -0700 Message-Id: <20211015041053.2769193-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- configure | 8 ++------ meson.build | 4 +--- linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++-- linux-user/host/riscv32/hostdep.h | 11 ----------- linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0 5 files changed, 5 insertions(+), 22 deletions(-) rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%) delete mode 100644 linux-user/host/riscv32/hostdep.h rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/configure b/configure index 039467c04b..d57ad58342 100755 --- a/configure +++ b/configure @@ -570,11 +570,7 @@ elif check_define __s390__ ; then cpu="s390" fi elif check_define __riscv ; then - if check_define _LP64 ; then - cpu="riscv64" - else - cpu="riscv32" - fi + cpu="riscv" elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then @@ -587,7 +583,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv) ;; ppc64le) ARCH="ppc64" diff --git a/meson.build b/meson.build index 6b7487b725..1a8fc2c4e0 100644 --- a/meson.build +++ b/meson.build @@ -52,7 +52,7 @@ have_block = have_system or have_tools python = import('python').find_installation() supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() @@ -342,8 +342,6 @@ if not get_option('tcg').disabled() tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' tcg_arch = 'ppc' - elif config_host['ARCH'] in ['riscv32', 'riscv64'] - tcg_arch = 'riscv' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch, language: ['c', 'cpp', 'objc']) diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/hostdep.h similarity index 94% rename from linux-user/host/riscv64/hostdep.h rename to linux-user/host/riscv/hostdep.h index 865f0fb9ff..2ba07456ae 100644 --- a/linux-user/host/riscv64/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ -#ifndef RISCV64_HOSTDEP_H -#define RISCV64_HOSTDEP_H +#ifndef RISCV_HOSTDEP_H +#define RISCV_HOSTDEP_H /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h deleted file mode 100644 index adf9edbf2d..0000000000 --- a/linux-user/host/riscv32/hostdep.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV32_HOSTDEP_H -#define RISCV32_HOSTDEP_H - -#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S similarity index 100% rename from linux-user/host/riscv64/safe-syscall.inc.S rename to linux-user/host/riscv/safe-syscall.inc.S