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[209.51.188.17]) by mx.google.com with ESMTPS id b9si6889346ilj.152.2021.10.14.21.40.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:40:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AzkuZD2w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbF1Z-0002Ih-0S for patch@linaro.org; Fri, 15 Oct 2021 00:40:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39550) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEc9-0006ko-VB for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:37 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:54255) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEc6-0002oI-Gz for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:14:37 -0400 Received: by mail-pj1-x102d.google.com with SMTP id ls18so6335513pjb.3 for ; Thu, 14 Oct 2021 21:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AiCyvdTR/3QA/VxcdfSHeMxoA2jAV+mFfUYWeOlFIz4=; b=AzkuZD2wasbwRAkK/Rm9AAlJbUBaieGLOuuv/TzRUq5RWybUIHzXtVVW2HtDVgac1n x8RXUqif3C9stTlp36sxcOM3StMDtjlI/A12QccAkhHSxVII999Xf4f+2JzEz/O/FG3w Df1j2G3PJqAeZl5r0DGuJWIwxYsFMAFRa3lAZqgABsf7hDYN2Gh1HowoXBybc8IoLj+d ooxbfW44K2/20DTZT4E5URUfqNKdlv7E8mn/AIaHJL1VIIy1aj+RlGCZMv5pP32aoyvF oVslzpCwX0A4OL71uRdYfke9NorMycj1eRtAGtkWAdPSOcEDi0AbUziN6kIWvQvyT3pE eiSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AiCyvdTR/3QA/VxcdfSHeMxoA2jAV+mFfUYWeOlFIz4=; b=E53rSLfe7/WNoGg+nobS4240GvlOGV1CenPmre3FtiRTmzb1jsnfDbsYcwB1dyksQa S2Ku+SaSk9yYCmRmN1Vgk5YuJ38AN9z6CHykTI8XfmQ92Ryd81n/SguYMOZ8mxpzN/f9 e3+e2JeQg/4baxJIQQ9KV71NkRQxKV7rW/INccHtkn7euWiHMX+pc1mXwm53fkAvM8Q+ lR4OeXHy4f2MMSi5vownpBx/ZIVsSoba47OAQn3xxrjzzMI4opw4Hwyf2eDxO36vzY9s Qe9ubIvpatxqbcmomn4RYegWDdc8zJYqX508fgcNgY1aYoF/yymSxcxVBRhy491hukVm qpcw== X-Gm-Message-State: AOAM530QumXklisqlofGUM3VTaU4xEs4luChvxX1TFWUri2SdtwU6Uu4 OtnGorQ37fUS4+29buzJbPkJeUVSt+pgwQ== X-Received: by 2002:a17:90a:3b49:: with SMTP id t9mr24795706pjf.218.1634271272144; Thu, 14 Oct 2021 21:14:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q8sm10236885pja.52.2021.10.14.21.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:14:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus Date: Thu, 14 Oct 2021 21:10:32 -0700 Message-Id: <20211015041053.2769193-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because of the complexity of setting ESR, re-use the existing arm_cpu_do_unaligned_access function. This means we have to handle the exception ourselves in cpu_loop, transforming it to the appropriate signal. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ linux-user/aarch64/cpu_loop.c | 12 +++++++++--- linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++---- target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/tlb_helper.c | 6 ++++++ 6 files changed, 45 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a7aaf0f51..89f7610ebc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result) void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); +void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, + MMUAccessType access_type, uintptr_t ra); #else bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 034b737435..97e0728b67 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -79,7 +79,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_code, si_signo; abi_long ret; for (;;) { @@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env) fsc = extract32(env->exception.syndrome, 0, 6); switch (fsc) { case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MAPERR; break; case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_ACCERR; break; case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; si_code = TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress); + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ae09adcb95..01cb6eb534 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -25,6 +25,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, si_signo, si_code; unsigned int n, insn; abi_ulong ret; @@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a18a58ca0..a211804fd3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 7b3bea2fbb..13d0e9b195 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv, + .record_sigbus = arm_cpu_record_sigbus, #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index dc5860180f..12a934e924 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, cpu_restore_state(cs, ra, true); arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi); } + +void arm_cpu_record_sigbus(CPUState *cs, vaddr addr, + MMUAccessType access_type, uintptr_t ra) +{ + arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra); +} #endif /* !defined(CONFIG_USER_ONLY) */