| Message ID | 20211015041053.2769193-36-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | user-only: Cleanup SIGSEGV and SIGBUS handling | expand |
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson < richard.henderson@linaro.org> wrote: > The fallback code in cpu_loop_exit_sigsegv is sufficient > for riscv linux-user. > > Remove the code from cpu_loop that raised SIGSEGV. > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > linux-user/riscv/cpu_loop.c | 7 ------- > target/riscv/cpu.c | 2 +- > target/riscv/cpu_helper.c | 21 +-------------------- > 3 files changed, 2 insertions(+), 28 deletions(-) > Reviewed-by: Warner Losh <imp@bsdimp.com> > diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c > index 9859a366e4..aef019b1c8 100644 > --- a/linux-user/riscv/cpu_loop.c > +++ b/linux-user/riscv/cpu_loop.c > @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) > sigcode = TARGET_TRAP_BRKPT; > sigaddr = env->pc; > break; > - case RISCV_EXCP_INST_PAGE_FAULT: > - case RISCV_EXCP_LOAD_PAGE_FAULT: > - case RISCV_EXCP_STORE_PAGE_FAULT: > - signum = TARGET_SIGSEGV; > - sigcode = TARGET_SEGV_MAPERR; > - sigaddr = env->badaddr; > - break; > case RISCV_EXCP_SEMIHOST: > env->gpr[xA0] = do_common_semihosting(cs); > env->pc += 4; > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1d69d1887e..2ab89a3f70 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -653,9 +653,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { > static const struct TCGCPUOps riscv_tcg_ops = { > .initialize = riscv_translate_init, > .synchronize_from_tb = riscv_cpu_synchronize_from_tb, > - .tlb_fill = riscv_cpu_tlb_fill, > > #ifndef CONFIG_USER_ONLY > + .tlb_fill = riscv_cpu_tlb_fill, > .cpu_exec_interrupt = riscv_cpu_exec_interrupt, > .do_interrupt = riscv_cpu_do_interrupt, > .do_transaction_failed = riscv_cpu_do_transaction_failed, > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index d41d5cd27c..b520d6fc78 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr > addr, > riscv_cpu_two_stage_lookup(mmu_idx); > riscv_raise_exception(env, cs->exception_index, retaddr); > } > -#endif /* !CONFIG_USER_ONLY */ > > bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, > int size, > { > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > -#ifndef CONFIG_USER_ONLY > vaddr im_address; > hwaddr pa = 0; > int prot, prot2, prot_pmp; > @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, > int size, > } > > return true; > - > -#else > - switch (access_type) { > - case MMU_INST_FETCH: > - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; > - break; > - case MMU_DATA_LOAD: > - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; > - break; > - case MMU_DATA_STORE: > - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; > - break; > - default: > - g_assert_not_reached(); > - } > - env->badaddr = address; > - cpu_loop_exit_restore(cs, retaddr); > -#endif > } > +#endif /* !CONFIG_USER_ONLY */ > > /* > * Handle Traps > -- > 2.25.1 > > <div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">The fallback code in cpu_loop_exit_sigsegv is sufficient<br> for riscv linux-user.<br> <br> Remove the code from cpu_loop that raised SIGSEGV.<br> <br> Reviewed-by: Alistair Francis <<a href="mailto:alistair.francis@wdc.com" target="_blank">alistair.francis@wdc.com</a>><br> Reviewed-by: Philippe Mathieu-Daudé <<a href="mailto:f4bug@amsat.org" target="_blank">f4bug@amsat.org</a>><br> Signed-off-by: Richard Henderson <<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>><br> ---<br> linux-user/riscv/cpu_loop.c | 7 -------<br> target/riscv/cpu.c | 2 +-<br> target/riscv/cpu_helper.c | 21 +--------------------<br> 3 files changed, 2 insertions(+), 28 deletions(-)<br></blockquote><div><br></div><div><div>Reviewed-by: Warner Losh <<a href="mailto:imp@bsdimp.com">imp@bsdimp.com</a>></div></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c<br> index 9859a366e4..aef019b1c8 100644<br> --- a/linux-user/riscv/cpu_loop.c<br> +++ b/linux-user/riscv/cpu_loop.c<br> @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env)<br> sigcode = TARGET_TRAP_BRKPT;<br> sigaddr = env->pc;<br> break;<br> - case RISCV_EXCP_INST_PAGE_FAULT:<br> - case RISCV_EXCP_LOAD_PAGE_FAULT:<br> - case RISCV_EXCP_STORE_PAGE_FAULT:<br> - signum = TARGET_SIGSEGV;<br> - sigcode = TARGET_SEGV_MAPERR;<br> - sigaddr = env->badaddr;<br> - break;<br> case RISCV_EXCP_SEMIHOST:<br> env->gpr[xA0] = do_common_semihosting(cs);<br> env->pc += 4;<br> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c<br> index 1d69d1887e..2ab89a3f70 100644<br> --- a/target/riscv/cpu.c<br> +++ b/target/riscv/cpu.c<br> @@ -653,9 +653,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {<br> static const struct TCGCPUOps riscv_tcg_ops = {<br> .initialize = riscv_translate_init,<br> .synchronize_from_tb = riscv_cpu_synchronize_from_tb,<br> - .tlb_fill = riscv_cpu_tlb_fill,<br> <br> #ifndef CONFIG_USER_ONLY<br> + .tlb_fill = riscv_cpu_tlb_fill,<br> .cpu_exec_interrupt = riscv_cpu_exec_interrupt,<br> .do_interrupt = riscv_cpu_do_interrupt,<br> .do_transaction_failed = riscv_cpu_do_transaction_failed,<br> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c<br> index d41d5cd27c..b520d6fc78 100644<br> --- a/target/riscv/cpu_helper.c<br> +++ b/target/riscv/cpu_helper.c<br> @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,<br> riscv_cpu_two_stage_lookup(mmu_idx);<br> riscv_raise_exception(env, cs->exception_index, retaddr);<br> }<br> -#endif /* !CONFIG_USER_ONLY */<br> <br> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br> MMUAccessType access_type, int mmu_idx,<br> @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br> {<br> RISCVCPU *cpu = RISCV_CPU(cs);<br> CPURISCVState *env = &cpu->env;<br> -#ifndef CONFIG_USER_ONLY<br> vaddr im_address;<br> hwaddr pa = 0;<br> int prot, prot2, prot_pmp;<br> @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br> }<br> <br> return true;<br> -<br> -#else<br> - switch (access_type) {<br> - case MMU_INST_FETCH:<br> - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;<br> - break;<br> - case MMU_DATA_LOAD:<br> - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;<br> - break;<br> - case MMU_DATA_STORE:<br> - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;<br> - break;<br> - default:<br> - g_assert_not_reached();<br> - }<br> - env->badaddr = address;<br> - cpu_loop_exit_restore(cs, retaddr);<br> -#endif<br> }<br> +#endif /* !CONFIG_USER_ONLY */<br> <br> /*<br> * Handle Traps<br> -- <br> 2.25.1<br> <br> </blockquote></div></div>
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..aef019b1c8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_TRAP_BRKPT; sigaddr = env->pc; break; - case RISCV_EXCP_INST_PAGE_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - signum = TARGET_SIGSEGV; - sigcode = TARGET_SEGV_MAPERR; - sigaddr = env->badaddr; - break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] = do_common_semihosting(cs); env->pc += 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..2ab89a3f70 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -653,9 +653,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = riscv_cpu_tlb_fill, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..b520d6fc78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; int prot, prot2, prot_pmp; @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } return true; - -#else - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; - break; - default: - g_assert_not_reached(); - } - env->badaddr = address; - cpu_loop_exit_restore(cs, retaddr); -#endif } +#endif /* !CONFIG_USER_ONLY */ /* * Handle Traps