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[209.51.188.17]) by mx.google.com with ESMTPS id s128si5632846ybb.78.2021.10.14.21.33.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:33:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Yov1R+NL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEus-000413-GM for patch@linaro.org; Fri, 15 Oct 2021 00:33:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEZ2-0007No-LU for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:24 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:34605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYw-0000Nj-Hv for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:23 -0400 Received: by mail-pg1-x530.google.com with SMTP id 133so7465770pgb.1 for ; Thu, 14 Oct 2021 21:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=Yov1R+NL044SWENOR1xG+VONSMx58VYed3LLoUluBL2dM/Wpek9T8T16O7dkctxn7J ND58+ed9JcpXTNwEj3XfFWQdDtKlnw8cPTsmnvPt52Q9atGaKQQwG1n18UIC93r7uULA 9awjU3UnOFXRyi/YNs0Ik/eC1MjtkMmPPaML83cWiMXjK2NqdsE1PFe6u+7sx7ciyRIx /6FSrv+hTJ9pMn+giMKD4jV3HYmY8yCxCl/iWXpMmKGJVh0AVd/Cisb9J7KDzNPp83aZ JYT3xPHU+MQZtWST7kBnG/pV78VbXJqn8+OZRUTw/Pzj6yrEfLxKmzsD/JV6rn5hPHyz s+iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xDn64Ar0c4NUi8qPBLq+7M9+nijncdxsp88/28xGJnw=; b=3hBA1WE0rZ/PzZepRb8tYibxQtLmciBNqXHvoOXiBoPl9BkdSKjnMpdHmhPJtFmcS0 2SubHS7qdsNrGjn+lMkep/w0U508YwhhXfl2t528J2QMJ3XWnYsZ0JwgIq93O+awWuju uRLdQs3+NPFDTVSjj4nad8Kswbz6Qb1eflKc9isXIUrt3PneeLoOJeECSql9qRXwEc7m Fa3be278VIA3VVkBNl7R5KE4gss8Wn4bogKJYPWYoavRRS8+lcz6qpr+6+ezjvM74+it RL8XWAqghrZwu6jFJO7KMA+Q2QtqPDBlbHCew5deRkGnOnrYMHQR91KmBUdCiQyMFXkx Ulwg== X-Gm-Message-State: AOAM533AheQ08wQ2svfBPDQzmTl4+zkTdONYuvWbFTzU4X3ppxm16lhk U5/6axH/oz/pN4a0bQkABm98+OE/wxIHcQ== X-Received: by 2002:a63:d94b:: with SMTP id e11mr7211521pgj.295.1634271076937; Thu, 14 Oct 2021 21:11:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only Date: Thu, 14 Oct 2021 21:10:12 -0700 Message-Id: <20211015041053.2769193-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fallback code in cpu_loop_exit_sigsegv is sufficient for hppa linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- linux-user/hppa/cpu_loop.c | 16 ---------------- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 15 --------------- target/hppa/meson.build | 6 ++++-- 5 files changed, 6 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d3cb7a279f..294fd7297f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +#ifndef CONFIG_USER_ONLY bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -#ifndef CONFIG_USER_ONLY void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 81607a9b27..e0a62deeb9 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case EXCP_ITLB_MISS: - case EXCP_DTLB_MISS: - case EXCP_NA_ITLB_MISS: - case EXCP_NA_DTLB_MISS: - case EXCP_IMP: - case EXCP_DMP: - case EXCP_DMB: - case EXCP_PAGE_REF: - case EXCP_DMAR: - case EXCP_DMPI: - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_ACCERR; - info._sifields._sigfault._addr = env->cr[CR_IOR]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; case EXCP_UNALIGN: info.si_signo = TARGET_SIGBUS; info.si_errno = 0; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 89cba9d7a2..23eb254228 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, - .tlb_fill = hppa_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .tlb_fill = hppa_cpu_tlb_fill, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index afc5b56c3e..bf07445cd1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,20 +24,6 @@ #include "hw/core/cpu.h" #include "trace.h" -#ifdef CONFIG_USER_ONLY -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - HPPACPU *cpu = HPPA_CPU(cs); - - /* ??? Test between data page fault and data memory protection trap, - which would affect si_code. */ - cs->exception_index = EXCP_DMP; - cpu->env.cr[CR_IOR] = address; - cpu_loop_exit_restore(cs, retaddr); -} -#else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } -#endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..021e42a2d0 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -7,13 +7,15 @@ hppa_ss.add(files( 'gdbstub.c', 'helper.c', 'int_helper.c', - 'mem_helper.c', 'op_helper.c', 'translate.c', )) hppa_softmmu_ss = ss.source_set() -hppa_softmmu_ss.add(files('machine.c')) +hppa_softmmu_ss.add(files( + 'machine.c', + 'mem_helper.c', +)) target_arch += {'hppa': hppa_ss} target_softmmu_arch += {'hppa': hppa_softmmu_ss}