| Message ID | 20211015041053.2769193-15-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | user-only: Cleanup SIGSEGV and SIGBUS handling | expand |
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson < richard.henderson@linaro.org> wrote: > Split host_signal_pc and host_signal_write out of user-exec.c. > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- > accel/tcg/user-exec.c | 52 +------------------------ > 2 files changed, 62 insertions(+), 52 deletions(-) > Reviewed-by: Warner Losh <imp@bsdimp.com> > diff --git a/linux-user/host/mips/host-signal.h > b/linux-user/host/mips/host-signal.h > index f4b4d65031..9c83e51130 100644 > --- a/linux-user/host/mips/host-signal.h > +++ b/linux-user/host/mips/host-signal.h > @@ -1 +1,61 @@ > -#define HOST_SIGNAL_PLACEHOLDER > +/* > + * host-signal.h: signal info dependent on the host architecture > + * > + * Copyright (C) 2021 Linaro Limited > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or > later. > + * See the COPYING file in the top-level directory. > + */ > + > +#ifndef MIPS_HOST_SIGNAL_H > +#define MIPS_HOST_SIGNAL_H > + > +static inline uintptr_t host_signal_pc(ucontext_t *uc) > +{ > + return uc->uc_mcontext.pc; > +} > + > +#if defined(__misp16) || defined(__mips_micromips) > +#error "Unsupported encoding" > +#endif > + > +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) > +{ > + uint32_t insn = *(uint32_t *)host_signal_pc(uc); > + > + /* Detect all store instructions at program counter. */ > + switch ((insn >> 26) & 077) { > + case 050: /* SB */ > + case 051: /* SH */ > + case 052: /* SWL */ > + case 053: /* SW */ > + case 054: /* SDL */ > + case 055: /* SDR */ > + case 056: /* SWR */ > + case 070: /* SC */ > + case 071: /* SWC1 */ > + case 074: /* SCD */ > + case 075: /* SDC1 */ > + case 077: /* SD */ > +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 > + case 072: /* SWC2 */ > + case 076: /* SDC2 */ > +#endif > + return true; > + case 023: /* COP1X */ > + /* > + * Required in all versions of MIPS64 since > + * MIPS64r1 and subsequent versions of MIPS32r2. > + */ > + switch (insn & 077) { > + case 010: /* SWXC1 */ > + case 011: /* SDXC1 */ > + case 015: /* SUXC1 */ > + return true; > + } > + break; > + } > + return false; > +} > + > +#endif > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c > index bfd964b578..287f03dac5 100644 > --- a/accel/tcg/user-exec.c > +++ b/accel/tcg/user-exec.c > @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong > addr, int size, > return size ? g2h(env_cpu(env), addr) : NULL; > } > > -#if defined(__mips__) > - > -#if defined(__misp16) || defined(__mips_micromips) > -#error "Unsupported encoding" > -#endif > - > -int cpu_signal_handler(int host_signum, void *pinfo, > - void *puc) > -{ > - siginfo_t *info = pinfo; > - ucontext_t *uc = puc; > - uintptr_t pc = uc->uc_mcontext.pc; > - uint32_t insn = *(uint32_t *)pc; > - int is_write = 0; > - > - /* Detect all store instructions at program counter. */ > - switch((insn >> 26) & 077) { > - case 050: /* SB */ > - case 051: /* SH */ > - case 052: /* SWL */ > - case 053: /* SW */ > - case 054: /* SDL */ > - case 055: /* SDR */ > - case 056: /* SWR */ > - case 070: /* SC */ > - case 071: /* SWC1 */ > - case 074: /* SCD */ > - case 075: /* SDC1 */ > - case 077: /* SD */ > -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 > - case 072: /* SWC2 */ > - case 076: /* SDC2 */ > -#endif > - is_write = 1; > - break; > - case 023: /* COP1X */ > - /* Required in all versions of MIPS64 since > - MIPS64r1 and subsequent versions of MIPS32r2. */ > - switch (insn & 077) { > - case 010: /* SWXC1 */ > - case 011: /* SDXC1 */ > - case 015: /* SUXC1 */ > - is_write = 1; > - } > - break; > - } > - > - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); > -} > - > -#elif defined(__riscv) > +#if defined(__riscv) > > int cpu_signal_handler(int host_signum, void *pinfo, > void *puc) > -- > 2.25.1 > > <div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Split host_signal_pc and host_signal_write out of user-exec.c.<br> <br> Reviewed-by: Philippe Mathieu-Daudé <<a href="mailto:f4bug@amsat.org" target="_blank">f4bug@amsat.org</a>><br> Signed-off-by: Richard Henderson <<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>><br> ---<br> linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++-<br> accel/tcg/user-exec.c | 52 +------------------------<br> 2 files changed, 62 insertions(+), 52 deletions(-)<br></blockquote><div><br></div><div><div>Reviewed-by: Warner Losh <<a href="mailto:imp@bsdimp.com">imp@bsdimp.com</a>></div><br class="gmail-Apple-interchange-newline"></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h<br> index f4b4d65031..9c83e51130 100644<br> --- a/linux-user/host/mips/host-signal.h<br> +++ b/linux-user/host/mips/host-signal.h<br> @@ -1 +1,61 @@<br> -#define HOST_SIGNAL_PLACEHOLDER<br> +/*<br> + * host-signal.h: signal info dependent on the host architecture<br> + *<br> + * Copyright (C) 2021 Linaro Limited<br> + *<br> + * This work is licensed under the terms of the GNU GPL, version 2 or later.<br> + * See the COPYING file in the top-level directory.<br> + */<br> +<br> +#ifndef MIPS_HOST_SIGNAL_H<br> +#define MIPS_HOST_SIGNAL_H<br> +<br> +static inline uintptr_t host_signal_pc(ucontext_t *uc)<br> +{<br> + return uc->uc_mcontext.pc;<br> +}<br> +<br> +#if defined(__misp16) || defined(__mips_micromips)<br> +#error "Unsupported encoding"<br> +#endif<br> +<br> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)<br> +{<br> + uint32_t insn = *(uint32_t *)host_signal_pc(uc);<br> +<br> + /* Detect all store instructions at program counter. */<br> + switch ((insn >> 26) & 077) {<br> + case 050: /* SB */<br> + case 051: /* SH */<br> + case 052: /* SWL */<br> + case 053: /* SW */<br> + case 054: /* SDL */<br> + case 055: /* SDR */<br> + case 056: /* SWR */<br> + case 070: /* SC */<br> + case 071: /* SWC1 */<br> + case 074: /* SCD */<br> + case 075: /* SDC1 */<br> + case 077: /* SD */<br> +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6<br> + case 072: /* SWC2 */<br> + case 076: /* SDC2 */<br> +#endif<br> + return true;<br> + case 023: /* COP1X */<br> + /*<br> + * Required in all versions of MIPS64 since<br> + * MIPS64r1 and subsequent versions of MIPS32r2.<br> + */<br> + switch (insn & 077) {<br> + case 010: /* SWXC1 */<br> + case 011: /* SDXC1 */<br> + case 015: /* SUXC1 */<br> + return true;<br> + }<br> + break;<br> + }<br> + return false;<br> +}<br> +<br> +#endif<br> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c<br> index bfd964b578..287f03dac5 100644<br> --- a/accel/tcg/user-exec.c<br> +++ b/accel/tcg/user-exec.c<br> @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,<br> return size ? g2h(env_cpu(env), addr) : NULL;<br> }<br> <br> -#if defined(__mips__)<br> -<br> -#if defined(__misp16) || defined(__mips_micromips)<br> -#error "Unsupported encoding"<br> -#endif<br> -<br> -int cpu_signal_handler(int host_signum, void *pinfo,<br> - void *puc)<br> -{<br> - siginfo_t *info = pinfo;<br> - ucontext_t *uc = puc;<br> - uintptr_t pc = uc->uc_mcontext.pc;<br> - uint32_t insn = *(uint32_t *)pc;<br> - int is_write = 0;<br> -<br> - /* Detect all store instructions at program counter. */<br> - switch((insn >> 26) & 077) {<br> - case 050: /* SB */<br> - case 051: /* SH */<br> - case 052: /* SWL */<br> - case 053: /* SW */<br> - case 054: /* SDL */<br> - case 055: /* SDR */<br> - case 056: /* SWR */<br> - case 070: /* SC */<br> - case 071: /* SWC1 */<br> - case 074: /* SCD */<br> - case 075: /* SDC1 */<br> - case 077: /* SD */<br> -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6<br> - case 072: /* SWC2 */<br> - case 076: /* SDC2 */<br> -#endif<br> - is_write = 1;<br> - break;<br> - case 023: /* COP1X */<br> - /* Required in all versions of MIPS64 since<br> - MIPS64r1 and subsequent versions of MIPS32r2. */<br> - switch (insn & 077) {<br> - case 010: /* SWXC1 */<br> - case 011: /* SDXC1 */<br> - case 015: /* SUXC1 */<br> - is_write = 1;<br> - }<br> - break;<br> - }<br> -<br> - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);<br> -}<br> -<br> -#elif defined(__riscv)<br> +#if defined(__riscv)<br> <br> int cpu_signal_handler(int host_signum, void *pinfo,<br> void *puc)<br> -- <br> 2.25.1<br> <br> </blockquote></div></div>
diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h index f4b4d65031..9c83e51130 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -1 +1,61 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_HOST_SIGNAL_H +#define MIPS_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.pc; +} + +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + uint32_t insn = *(uint32_t *)host_signal_pc(uc); + + /* Detect all store instructions at program counter. */ + switch ((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + return true; + case 023: /* COP1X */ + /* + * Required in all versions of MIPS64 since + * MIPS64r1 and subsequent versions of MIPS32r2. + */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + return true; + } + break; + } + return false; +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bfd964b578..287f03dac5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__mips__) - -#if defined(__misp16) || defined(__mips_micromips) -#error "Unsupported encoding" -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; - ucontext_t *uc = puc; - uintptr_t pc = uc->uc_mcontext.pc; - uint32_t insn = *(uint32_t *)pc; - int is_write = 0; - - /* Detect all store instructions at program counter. */ - switch((insn >> 26) & 077) { - case 050: /* SB */ - case 051: /* SH */ - case 052: /* SWL */ - case 053: /* SW */ - case 054: /* SDL */ - case 055: /* SDR */ - case 056: /* SWR */ - case 070: /* SC */ - case 071: /* SWC1 */ - case 074: /* SCD */ - case 075: /* SDC1 */ - case 077: /* SD */ -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 - case 072: /* SWC2 */ - case 076: /* SDC2 */ -#endif - is_write = 1; - break; - case 023: /* COP1X */ - /* Required in all versions of MIPS64 since - MIPS64r1 and subsequent versions of MIPS32r2. */ - switch (insn & 077) { - case 010: /* SWXC1 */ - case 011: /* SDXC1 */ - case 015: /* SUXC1 */ - is_write = 1; - } - break; - } - - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__riscv) +#if defined(__riscv) int cpu_signal_handler(int host_signum, void *pinfo, void *puc)