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[209.51.188.17]) by mx.google.com with ESMTPS id c6si5229926ybi.367.2021.10.14.21.14.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Oct 2021 21:14:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LOcVIOc7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbEc6-00048j-MS for patch@linaro.org; Fri, 15 Oct 2021 00:14:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbEYo-00073Q-Mr for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:10 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:42658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbEYk-0000DH-JJ for qemu-devel@nongnu.org; Fri, 15 Oct 2021 00:11:09 -0400 Received: by mail-pg1-x52d.google.com with SMTP id 66so7428043pgc.9 for ; Thu, 14 Oct 2021 21:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=btQGr7frnhamoWbiryuObxAGescEK943qi/jomZ8OHU=; b=LOcVIOc75Hq+kR/jqzxLv5knGddqUvREHUK6bsG3NLRWE9o3j+QZK1RHv0uvJToLrH CdUxeuflbLSg1BNaxg0kZ4X5fCJuwgqrQLAbNj54PgmNFoLqMBZ1DvBlrJQcMoUTgwxM GbO3jmlbu4oG7XJ65ErxtnlT2l67JJUcVCgdGWMYQJZPQE1A/ztDKgNAYjdgcMtBoU2i I6l8E0wPG8BDTyCLbfQUhjiICslS5b5w+XHeSFFoCnShnSA2L3Ib0S8ZCwnxmZic/l7K J4281W028D40ps8IctR74UUa6fYYXUT2a4Tcs/bSJKKSlkB1RZjjZqE6S/4Ji7eYyHxW hvmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=btQGr7frnhamoWbiryuObxAGescEK943qi/jomZ8OHU=; b=yIKneaH1BPcYmVif+aPLAG/C+XMvnOWHGwpKm+XoNfRCjdLeDGR2NIubg7F8Xpi1He ouKnSG+DJmmhk/bj03rUgRHnBXcHdo6hMS3K8Kql3sKru3H3CvYohcefKfhhg99YPnHx HXf27FVQyK7RZPj5yOBII/S9+3T8KLSMVjcYCTxA78d/HoF90OXSFBplxSiKBaEdj9Fr 2UtqhUQVPVs1NYjEsCPmsqghc1YI0IR/UZkXaSc2BTX0dy+jb0p57CQ4Lj+kmo60S6RP stEHA/80xtWgeMJ26Bl7OM0If16aATg51EpocYWCcrtz5CmgFMPXSD5aoMv9njbS+vfL LESg== X-Gm-Message-State: AOAM5333+VnuIo8aYXnVqE+VApyvnPICtf2mI6N0aEbJBI0IHoY9+K8b 2vlZEwz8Yd1THtk7Qv3MwYTgOq4AkyI= X-Received: by 2002:a63:2a92:: with SMTP id q140mr7429126pgq.412.1634271065178; Thu, 14 Oct 2021 21:11:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id me12sm5718006pjb.27.2021.10.14.21.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 21:11:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/67] linux-user/host/arm: Populate host_signal.h Date: Thu, 14 Oct 2021 21:09:57 -0700 Message-Id: <20211015041053.2769193-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015041053.2769193-1-richard.henderson@linaro.org> References: <20211015041053.2769193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com, =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- accel/tcg/user-exec.c | 45 +------------------------------ 2 files changed, 30 insertions(+), 45 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr = uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 17fe867aeb..5656c654e1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__arm__) - -#if defined(__NetBSD__) -#include -#include -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) - ucontext_t *uc = puc; - siginfo_t *si = pinfo; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc = uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) - pc = uc->uc_mcontext.gregs[R15]; -#else - pc = uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr = si->si_trap; -#else - fsr = uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write = extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) #if defined(__NetBSD__)