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[209.51.188.17]) by mx.google.com with ESMTPS id f10si170252qkp.289.2021.10.13.11.27.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Oct 2021 11:27:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=umokdoSe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52304 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maiyN-0001DM-KS for patch@linaro.org; Wed, 13 Oct 2021 14:27:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maiu1-0003xR-TD for qemu-devel@nongnu.org; Wed, 13 Oct 2021 14:22:57 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:53015) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maitz-00035j-8z for qemu-devel@nongnu.org; Wed, 13 Oct 2021 14:22:57 -0400 Received: by mail-pj1-x1032.google.com with SMTP id oa4so2905786pjb.2 for ; Wed, 13 Oct 2021 11:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=slyF7IqLapKeWo1JxWwPfUqGwcDiZ/hynums2qQtXjA=; b=umokdoSeS9ZN2vW7xLzzoZoGirughpcN9SY+YTbdUUBJpJO/iX3J4UbZXytvrBoHKl yaD2TwthyP9ByhSTPbWwvkl/t+3jCCJvI7ywhtn5e9kfS09OSeop3nqIUQzmtl6e/5QY U3iMTSRm4ba/ndTHuYkcJAq7wKBEOfXix2ND11n0PRAonoTBbvsv+4fuP4k2q0C9lMDs ihc6tUStBJnT8vvjE09z5+30pC4bvrB0Wk8MHenYTMOqmLVUeyrF7ZZiNLxtKhBE8xhI 9t17mpm16/kxtBGMoDB0URpjFTtQYUnVSWAE45uK8uT+TjhXA8jY/oVWI9MzdHoR7c6C irSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=slyF7IqLapKeWo1JxWwPfUqGwcDiZ/hynums2qQtXjA=; b=31pWp0mNURSC82QUotVOk6/dSHU1utKS+uemb1KT5re+GQoy9vEJ680hdx4bifx0fi isxHYmkJqCxsvzRKr07nHt10UdqsVSxJc88CPCOJUVfwyrgvGXnC2gjK5oT1G0Jn/Azc m1WJL46kiNRVaugNxoMFIL0x4LEB78HbsvESvy/gqw4pk+nXyrhcWE0QNWl1rA//e5N+ pscNSk40AZaA4QTLSQTzKZBKaI7vyNCBye1ic/UZ9GAhxcbVMzBCsvf4X/UxGMJ8cGTR ZvTwM5uj6wPHdV3ckaAe/tU3p6CboXolBfrVQ/AgPwZR1sKlgm+Mdcj9Tv4O/aXdGIJ2 Co/w== X-Gm-Message-State: AOAM530gfKl9+9BLhO25pRMGIQKSX5SWG096S7/yppxsX7veKSRdX/gS VRJ9foiLr3CSBtE5xuHglYrPLefA8Evvrw== X-Received: by 2002:a17:90a:428e:: with SMTP id p14mr15343437pjg.92.1634149373654; Wed, 13 Oct 2021 11:22:53 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id z2sm177140pfe.210.2021.10.13.11.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 11:22:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/15] target/mips: Use 8-byte memory ops for msa load/store Date: Wed, 13 Oct 2021 11:22:34 -0700 Message-Id: <20211013182239.991127-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org> References: <20211013182239.991127-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than use 4-16 separate operations, use 2 operations plus some byte reordering as necessary. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 201 +++++++++++++---------------------- 1 file changed, 71 insertions(+), 130 deletions(-) -- 2.25.1 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index a8880ce81c..e40c1b7057 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8218,47 +8218,31 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, #define MEMOP_IDX(DF) #endif +#ifdef TARGET_WORDS_BIGENDIAN +static inline uint64_t bswap16x4(uint64_t x) +{ + uint64_t m = 0x00ff00ff00ff00ffull; + return ((x & m) << 8) | ((x >> 8) & m); +} + +static inline uint64_t bswap32x2(uint64_t x) +{ + return ror64(bswap64(x), 32); +} +#endif + void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[1] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[2] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[3] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[4] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[5] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[6] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[7] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[8] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); - pwd->b[9] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[10] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[11] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[12] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[13] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[14] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[15] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); -#else - pwd->b[0] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[1] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[2] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[3] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[4] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[5] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[6] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[7] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[8] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); - pwd->b[9] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[10] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[11] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[12] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[13] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[14] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[15] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); -#endif + /* Load 8 bytes at a time. Vector element ordering makes this LE. */ + d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); + pwd->d[0] = d0; + pwd->d[1] = d1; } void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, @@ -8266,26 +8250,20 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[1] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[2] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[3] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[4] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); - pwd->h[5] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[6] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[7] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); -#else - pwd->h[0] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[1] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[2] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[3] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[4] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); - pwd->h[5] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[6] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[7] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then swap the four halfwords. + */ + d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap16x4(d0); + d1 = bswap16x4(d1); #endif + pwd->d[0] = d0; + pwd->d[1] = d1; } void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, @@ -8293,18 +8271,20 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[1] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[2] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); - pwd->w[3] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); -#else - pwd->w[0] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[1] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[2] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); - pwd->w[3] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then bswap the two words. + */ + d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap32x2(d0); + d1 = bswap32x2(d1); #endif + pwd->d[0] = d0; + pwd->d[1] = d1; } void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, @@ -8312,9 +8292,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); uintptr_t ra = GETPC(); + uint64_t d0, d1; - pwd->d[0] = cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra); - pwd->d[1] = cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra); + d0 = cpu_ldq_data_ra(env, addr + 0, ra); + d1 = cpu_ldq_data_ra(env, addr + 8, ra); + pwd->d[0] = d0; + pwd->d[1] = d1; } #define MSA_PAGESPAN(x) \ @@ -8344,41 +8327,9 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, ensure_writable_pages(env, addr, mmu_idx, ra); -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra); -#else - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra); -#endif + /* Store 8 bytes at a time. Vector element ordering makes this LE. */ + cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra); } void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, @@ -8387,28 +8338,19 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); uintptr_t ra = GETPC(); + uint64_t d0, d1; ensure_writable_pages(env, addr, mmu_idx, ra); -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra); -#else - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra); + /* Store 8 bytes at a time. See helper_msa_ld_h. */ + d0 = pwd->d[0]; + d1 = pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap16x4(d0); + d1 = bswap16x4(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, @@ -8417,20 +8359,19 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); int mmu_idx = cpu_mmu_index(env, false); uintptr_t ra = GETPC(); + uint64_t d0, d1; ensure_writable_pages(env, addr, mmu_idx, ra); -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra); -#else - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra); + /* Store 8 bytes at a time. See helper_msa_ld_w. */ + d0 = pwd->d[0]; + d1 = pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 = bswap32x2(d0); + d1 = bswap32x2(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, @@ -8442,6 +8383,6 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, ensure_writable_pages(env, addr, mmu_idx, GETPC()); - cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra); - cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra); + cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra); }