| Message ID | 20211010174401.141339-9-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg: support 32-bit guest addresses as signed | expand |
On 10/10/21 19:44, Richard Henderson wrote: > All RV64 32-bit operations sign-extend the output, so we are easily > able to keep TCG_TYPE_I32 values sign-extended in host registers. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/riscv/tcg-target-sa32.h | 6 +++++- > tcg/riscv/tcg-target.c.inc | 8 ++------ > 2 files changed, 7 insertions(+), 7 deletions(-) Nice. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Mon, Oct 11, 2021 at 3:50 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > All RV64 32-bit operations sign-extend the output, so we are easily > able to keep TCG_TYPE_I32 values sign-extended in host registers. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/riscv/tcg-target-sa32.h | 6 +++++- > tcg/riscv/tcg-target.c.inc | 8 ++------ > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h > index cb185b1526..703467b37a 100644 > --- a/tcg/riscv/tcg-target-sa32.h > +++ b/tcg/riscv/tcg-target-sa32.h > @@ -1 +1,5 @@ > -#define TCG_TARGET_SIGNED_ADDR32 0 > +/* > + * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32; > + * TCG expects this to only be set for 64-bit hosts. > + */ > +#define TCG_TARGET_SIGNED_ADDR32 (__riscv_xlen == 64) > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 9b13a46fb4..9426ef8926 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -952,10 +952,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, > tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); > > /* TLB Hit - translate address using addend. */ > - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { > - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); > - addrl = TCG_REG_TMP0; > - } > tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); > } > > @@ -1126,7 +1122,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) > data_regl, data_regh, addr_regl, addr_regh, > s->code_ptr, label_ptr); > #else > - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { > + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { > tcg_out_ext32u(s, base, addr_regl); > addr_regl = base; > } > @@ -1192,7 +1188,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) > data_regl, data_regh, addr_regl, addr_regh, > s->code_ptr, label_ptr); > #else > - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { > + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { > tcg_out_ext32u(s, base, addr_regl); > addr_regl = base; > } > -- > 2.25.1 > >
diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h index cb185b1526..703467b37a 100644 --- a/tcg/riscv/tcg-target-sa32.h +++ b/tcg/riscv/tcg-target-sa32.h @@ -1 +1,5 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +/* + * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32; + * TCG expects this to only be set for 64-bit hosts. + */ +#define TCG_TARGET_SIGNED_ADDR32 (__riscv_xlen == 64) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9b13a46fb4..9426ef8926 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -952,10 +952,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl = TCG_REG_TMP0; - } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); } @@ -1126,7 +1122,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } @@ -1192,7 +1188,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { tcg_out_ext32u(s, base, addr_regl); addr_regl = base; }
All RV64 32-bit operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target-sa32.h | 6 +++++- tcg/riscv/tcg-target.c.inc | 8 ++------ 2 files changed, 7 insertions(+), 7 deletions(-) -- 2.25.1