| Message ID | 20211010174401.141339-4-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg: support 32-bit guest addresses as signed | expand |
Hi Richard, On 2021/10/11 01:43, Richard Henderson wrote: > When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to > allow the 32-bit guest address to be sign extended within the > 64-bit host register instead of zero extended. > > This will simplify tcg hosts like MIPS, RISC-V, and LoongArch, > which naturally sign-extend 32-bit values, in contrast to x86_64 > and AArch64 which zero-extend them. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > accel/tcg/cputlb.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 761f726722..d12621c60e 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -39,6 +39,7 @@ > #ifdef CONFIG_PLUGIN > #include "qemu/plugin-memory.h" > #endif > +#include "tcg-target-sa32.h" > > /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ > /* #define DEBUG_TLB */ > @@ -92,6 +93,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) > > static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr) > { > + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) { It seems this branch's direction should always match that of the branch added below, so if TARGET_LONG_BITS == TARGET_LONG_BITS == 32 this invariant is broken? Or is this expected behavior? > + return tlb->addend + (int32_t)gaddr; > + } > return tlb->addend + (uintptr_t)gaddr; > } > > @@ -1234,7 +1238,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, > desc->iotlb[index].attrs = attrs; > > /* Now calculate the new entry */ > - tn.addend = addend - vaddr_page; > + > + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS < TCG_TARGET_REG_BITS) { > + tn.addend = addend - (int32_t)vaddr_page; > + } else { > + tn.addend = addend - vaddr_page; > + } > + > if (prot & PAGE_READ) { > tn.addr_read = address; > if (wp_flags & BP_MEM_READ) {
On 10/10/21 9:30 PM, WANG Xuerui wrote: >> @@ -92,6 +93,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) >> >> static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr) >> { >> + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) { > It seems this branch's direction should always match that of the branch > added below, so if TARGET_LONG_BITS == TARGET_LONG_BITS == 32 this > invariant is broken? Or is this expected behavior? The conditions should match, yes. In revising the patch set I decided that the tcg backend should simply not set this flag for a 32-bit host. r~
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 761f726722..d12621c60e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -39,6 +39,7 @@ #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif +#include "tcg-target-sa32.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -92,6 +93,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr) { + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) { + return tlb->addend + (int32_t)gaddr; + } return tlb->addend + (uintptr_t)gaddr; } @@ -1234,7 +1238,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, desc->iotlb[index].attrs = attrs; /* Now calculate the new entry */ - tn.addend = addend - vaddr_page; + + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS < TCG_TARGET_REG_BITS) { + tn.addend = addend - (int32_t)vaddr_page; + } else { + tn.addend = addend - vaddr_page; + } + if (prot & PAGE_READ) { tn.addr_read = address; if (wp_flags & BP_MEM_READ) {
When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to allow the 32-bit guest address to be sign extended within the 64-bit host register instead of zero extended. This will simplify tcg hosts like MIPS, RISC-V, and LoongArch, which naturally sign-extend 32-bit values, in contrast to x86_64 and AArch64 which zero-extend them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- accel/tcg/cputlb.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.25.1