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[68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/8] accel/tcg: Split out g2h_tlbe Date: Sun, 10 Oct 2021 10:43:55 -0700 Message-Id: <20211010174401.141339-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org> References: <20211010174401.141339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a new function to combine a CPUTLBEntry addend with the guest address to form a host address. Signed-off-by: Richard Henderson Reviewed-by: WANG Xuerui Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- accel/tcg/cputlb.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 46140ccff3..761f726722 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -90,6 +90,11 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) return fast->mask + (1 << CPU_TLB_ENTRY_BITS); } +static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr) +{ + return tlb->addend + (uintptr_t)gaddr; +} + static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, size_t max_entries) { @@ -976,8 +981,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) { - addr &= TARGET_PAGE_MASK; - addr += tlb_entry->addend; + addr = g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK); if ((addr - start) < length) { #if TCG_OVERSIZED_GUEST tlb_entry->addr_write |= TLB_NOTDIRTY; @@ -1527,7 +1531,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, return -1; } - p = (void *)((uintptr_t)addr + entry->addend); + p = (void *)g2h_tlbe(entry, addr); if (hostp) { *hostp = p; } @@ -1619,7 +1623,7 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, } /* Everything else is RAM. */ - *phost = (void *)((uintptr_t)addr + entry->addend); + *phost = (void *)g2h_tlbe(entry, addr); return flags; } @@ -1727,7 +1731,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx, data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; } else { data->is_io = false; - data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend); + data->v.ram.hostaddr = (void *)g2h_tlbe(tlbe, addr); } return true; } else { @@ -1826,7 +1830,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, goto stop_the_world; } - hostaddr = (void *)((uintptr_t)addr + tlbe->addend); + hostaddr = (void *)g2h_tlbe(tlbe, addr); if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, @@ -1938,7 +1942,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, access_type, op ^ (need_swap * MO_BSWAP)); } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); /* * Keep these two load_memop separate to ensure that the compiler @@ -1975,7 +1979,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); return load_memop(haddr, op); } @@ -2467,7 +2471,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); /* * Keep these two store_memop separate to ensure that the compiler @@ -2492,7 +2496,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); store_memop(haddr, val, op); }