diff mbox series

[01/13] target/riscv: Move cpu_get_tb_cpu_state out of line

Message ID 20211007174722.929993-2-richard.henderson@linaro.org
State Superseded
Headers show
Series target/riscv: Rationalize XLEN and operand length | expand

Commit Message

Richard Henderson Oct. 7, 2021, 5:47 p.m. UTC 
Move the function to cpu_helper.c, as it is large and growing.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/cpu.h        | 47 ++-------------------------------------
 target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 45 deletions(-)

-- 
2.25.1

Comments

Alistair Francis Oct. 8, 2021, 2:28 a.m. UTC | #1 
On Fri, Oct 8, 2021 at 3:52 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Move the function to cpu_helper.c, as it is large and growing.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


Alistair

> ---

>  target/riscv/cpu.h        | 47 ++-------------------------------------

>  target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++

>  2 files changed, 48 insertions(+), 45 deletions(-)

>

> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

> index 9e55b2f5b1..7084efc452 100644

> --- a/target/riscv/cpu.h

> +++ b/target/riscv/cpu.h

> @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)

>      return cpu->cfg.vlen >> (sew + 3 - lmul);

>  }

>

> -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,

> -                                        target_ulong *cs_base, uint32_t *pflags)

> -{

> -    uint32_t flags = 0;

> -

> -    *pc = env->pc;

> -    *cs_base = 0;

> -

> -    if (riscv_has_ext(env, RVV)) {

> -        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);

> -        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);

> -        flags = FIELD_DP32(flags, TB_FLAGS, VILL,

> -                    FIELD_EX64(env->vtype, VTYPE, VILL));

> -        flags = FIELD_DP32(flags, TB_FLAGS, SEW,

> -                    FIELD_EX64(env->vtype, VTYPE, VSEW));

> -        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,

> -                    FIELD_EX64(env->vtype, VTYPE, VLMUL));

> -        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);

> -    } else {

> -        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);

> -    }

> -

> -#ifdef CONFIG_USER_ONLY

> -    flags |= TB_FLAGS_MSTATUS_FS;

> -#else

> -    flags |= cpu_mmu_index(env, 0);

> -    if (riscv_cpu_fp_enabled(env)) {

> -        flags |= env->mstatus & MSTATUS_FS;

> -    }

> -

> -    if (riscv_has_ext(env, RVH)) {

> -        if (env->priv == PRV_M ||

> -            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

> -            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

> -                get_field(env->hstatus, HSTATUS_HU))) {

> -            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);

> -        }

> -

> -        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,

> -                           get_field(env->mstatus_hs, MSTATUS_FS));

> -    }

> -#endif

> -

> -    *pflags = flags;

> -}

> +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,

> +                          target_ulong *cs_base, uint32_t *pflags);

>

>  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,

>                             target_ulong *ret_value,

> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c

> index d41d5cd27c..14d1d3cb72 100644

> --- a/target/riscv/cpu_helper.c

> +++ b/target/riscv/cpu_helper.c

> @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)

>  #endif

>  }

>

> +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,

> +                          target_ulong *cs_base, uint32_t *pflags)

> +{

> +    uint32_t flags = 0;

> +

> +    *pc = env->pc;

> +    *cs_base = 0;

> +

> +    if (riscv_has_ext(env, RVV)) {

> +        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);

> +        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);

> +        flags = FIELD_DP32(flags, TB_FLAGS, VILL,

> +                    FIELD_EX64(env->vtype, VTYPE, VILL));

> +        flags = FIELD_DP32(flags, TB_FLAGS, SEW,

> +                    FIELD_EX64(env->vtype, VTYPE, VSEW));

> +        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,

> +                    FIELD_EX64(env->vtype, VTYPE, VLMUL));

> +        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);

> +    } else {

> +        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);

> +    }

> +

> +#ifdef CONFIG_USER_ONLY

> +    flags |= TB_FLAGS_MSTATUS_FS;

> +#else

> +    flags |= cpu_mmu_index(env, 0);

> +    if (riscv_cpu_fp_enabled(env)) {

> +        flags |= env->mstatus & MSTATUS_FS;

> +    }

> +

> +    if (riscv_has_ext(env, RVH)) {

> +        if (env->priv == PRV_M ||

> +            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

> +            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

> +                get_field(env->hstatus, HSTATUS_HU))) {

> +            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);

> +        }

> +

> +        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,

> +                           get_field(env->mstatus_hs, MSTATUS_FS));

> +    }

> +#endif

> +

> +    *pflags = flags;

> +}

> +

>  #ifndef CONFIG_USER_ONLY

>  static int riscv_cpu_local_irq_pending(CPURISCVState *env)

>  {

> --

> 2.25.1

>

>
LIU Zhiwei Oct. 13, 2021, 12:13 p.m. UTC | #2 
On 2021/10/8 上午1:47, Richard Henderson wrote:
> Move the function to cpu_helper.c, as it is large and growing.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>


Zhiwei
> ---

>   target/riscv/cpu.h        | 47 ++-------------------------------------

>   target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++

>   2 files changed, 48 insertions(+), 45 deletions(-)

>

> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

> index 9e55b2f5b1..7084efc452 100644

> --- a/target/riscv/cpu.h

> +++ b/target/riscv/cpu.h

> @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)

>       return cpu->cfg.vlen >> (sew + 3 - lmul);

>   }

>   

> -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,

> -                                        target_ulong *cs_base, uint32_t *pflags)

> -{

> -    uint32_t flags = 0;

> -

> -    *pc = env->pc;

> -    *cs_base = 0;

> -

> -    if (riscv_has_ext(env, RVV)) {

> -        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);

> -        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);

> -        flags = FIELD_DP32(flags, TB_FLAGS, VILL,

> -                    FIELD_EX64(env->vtype, VTYPE, VILL));

> -        flags = FIELD_DP32(flags, TB_FLAGS, SEW,

> -                    FIELD_EX64(env->vtype, VTYPE, VSEW));

> -        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,

> -                    FIELD_EX64(env->vtype, VTYPE, VLMUL));

> -        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);

> -    } else {

> -        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);

> -    }

> -

> -#ifdef CONFIG_USER_ONLY

> -    flags |= TB_FLAGS_MSTATUS_FS;

> -#else

> -    flags |= cpu_mmu_index(env, 0);

> -    if (riscv_cpu_fp_enabled(env)) {

> -        flags |= env->mstatus & MSTATUS_FS;

> -    }

> -

> -    if (riscv_has_ext(env, RVH)) {

> -        if (env->priv == PRV_M ||

> -            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

> -            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

> -                get_field(env->hstatus, HSTATUS_HU))) {

> -            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);

> -        }

> -

> -        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,

> -                           get_field(env->mstatus_hs, MSTATUS_FS));

> -    }

> -#endif

> -

> -    *pflags = flags;

> -}

> +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,

> +                          target_ulong *cs_base, uint32_t *pflags);

>   

>   RISCVException riscv_csrrw(CPURISCVState *env, int csrno,

>                              target_ulong *ret_value,

> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c

> index d41d5cd27c..14d1d3cb72 100644

> --- a/target/riscv/cpu_helper.c

> +++ b/target/riscv/cpu_helper.c

> @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)

>   #endif

>   }

>   

> +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,

> +                          target_ulong *cs_base, uint32_t *pflags)

> +{

> +    uint32_t flags = 0;

> +

> +    *pc = env->pc;

> +    *cs_base = 0;

> +

> +    if (riscv_has_ext(env, RVV)) {

> +        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);

> +        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);

> +        flags = FIELD_DP32(flags, TB_FLAGS, VILL,

> +                    FIELD_EX64(env->vtype, VTYPE, VILL));

> +        flags = FIELD_DP32(flags, TB_FLAGS, SEW,

> +                    FIELD_EX64(env->vtype, VTYPE, VSEW));

> +        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,

> +                    FIELD_EX64(env->vtype, VTYPE, VLMUL));

> +        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);

> +    } else {

> +        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);

> +    }

> +

> +#ifdef CONFIG_USER_ONLY

> +    flags |= TB_FLAGS_MSTATUS_FS;

> +#else

> +    flags |= cpu_mmu_index(env, 0);

> +    if (riscv_cpu_fp_enabled(env)) {

> +        flags |= env->mstatus & MSTATUS_FS;

> +    }

> +

> +    if (riscv_has_ext(env, RVH)) {

> +        if (env->priv == PRV_M ||

> +            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

> +            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

> +                get_field(env->hstatus, HSTATUS_HU))) {

> +            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);

> +        }

> +

> +        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,

> +                           get_field(env->mstatus_hs, MSTATUS_FS));

> +    }

> +#endif

> +

> +    *pflags = flags;

> +}

> +

>   #ifndef CONFIG_USER_ONLY

>   static int riscv_cpu_local_irq_pending(CPURISCVState *env)

>   {
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9e55b2f5b1..7084efc452 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -413,51 +413,8 @@  static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
     return cpu->cfg.vlen >> (sew + 3 - lmul);
 }
 
-static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-                                        target_ulong *cs_base, uint32_t *pflags)
-{
-    uint32_t flags = 0;
-
-    *pc = env->pc;
-    *cs_base = 0;
-
-    if (riscv_has_ext(env, RVV)) {
-        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
-        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-                    FIELD_EX64(env->vtype, VTYPE, VILL));
-        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
-                    FIELD_EX64(env->vtype, VTYPE, VSEW));
-        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
-                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
-        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
-    } else {
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
-    }
-
-#ifdef CONFIG_USER_ONLY
-    flags |= TB_FLAGS_MSTATUS_FS;
-#else
-    flags |= cpu_mmu_index(env, 0);
-    if (riscv_cpu_fp_enabled(env)) {
-        flags |= env->mstatus & MSTATUS_FS;
-    }
-
-    if (riscv_has_ext(env, RVH)) {
-        if (env->priv == PRV_M ||
-            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                get_field(env->hstatus, HSTATUS_HU))) {
-            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
-        }
-
-        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
-                           get_field(env->mstatus_hs, MSTATUS_FS));
-    }
-#endif
-
-    *pflags = flags;
-}
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                          target_ulong *cs_base, uint32_t *pflags);
 
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d41d5cd27c..14d1d3cb72 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -35,6 +35,52 @@  int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                          target_ulong *cs_base, uint32_t *pflags)
+{
+    uint32_t flags = 0;
+
+    *pc = env->pc;
+    *cs_base = 0;
+
+    if (riscv_has_ext(env, RVV)) {
+        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
+        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
+                    FIELD_EX64(env->vtype, VTYPE, VILL));
+        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
+                    FIELD_EX64(env->vtype, VTYPE, VSEW));
+        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
+                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
+        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
+    } else {
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
+    }
+
+#ifdef CONFIG_USER_ONLY
+    flags |= TB_FLAGS_MSTATUS_FS;
+#else
+    flags |= cpu_mmu_index(env, 0);
+    if (riscv_cpu_fp_enabled(env)) {
+        flags |= env->mstatus & MSTATUS_FS;
+    }
+
+    if (riscv_has_ext(env, RVH)) {
+        if (env->priv == PRV_M ||
+            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+                get_field(env->hstatus, HSTATUS_HU))) {
+            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
+        }
+
+        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
+                           get_field(env->mstatus_hs, MSTATUS_FS));
+    }
+#endif
+
+    *pflags = flags;
+}
+
 #ifndef CONFIG_USER_ONLY
 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
 {